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Implementation of time interleaved ADC based on delay line

Published: 17 April 2024 Publication History

Abstract

This article focuses on the study and design of a time-interleaved ADC (TIADC) utilizing delay lines. This approach has the advantage of using a cost-effective, multi-channel, low-speed ADC, thereby significantly reducing system costs. Furthermore, the implementation of time interleaving through signal delay eliminates the need for high-precision multi-phase clocks, further streamlining the system. To address the issue of channel frequency response mismatches within the TIADC and mitigate their impact on system performance, this paper employs a foreground calibration method based on perfect reconstruction theory. To assess the system's performance and the effectiveness of the calibration method, a 4-channel TIADC system with a 5GSPS sampling rate, designed using delay lines, is evaluated. Performance is measured in terms of signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR). The test results demonstrate that, after calibration, the SNR performance of the TIADC is improved by 3 to 10 dB, and the SFDR performance is enhanced by 5 to 20 dB.

References

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B. Razavi. 2013. Design Considerations for Interleaved ADCs. IEEE J. Solid-State Circuits. 48 (2013), pp.1806-1817. https://doi.org/ 10.1109/JSSC.2013.2258814
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AZEREDO-LEME C. 2011. Clock jitter effects on sampling: A tutorial. IEEE Circuits and Systems Magazine, 2011, 11(3): 26-37. https://doi.org/ 10.1109/MCAS.2011.942067.
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ELBORNSSON J, GUSTAFSSON F, EKLUND J E. 2004. Blind adaptive equalization of mismatch errors in a time-interleaved a/d converter system. IEEE Transactions on Circuits and Systems I: Regular Papers, 2004, 51(1): 151-158. https://doi.org/ 10.1109/TCSI.2003.821300
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SINGH S, ANTTILA L, EPP M, 2015. Frequency response mismatches in 4-channel time interleaved adcs: Analysis, blind identification, and correction. IEEE Transactions on Circuits and Systems I: Regular Papers, 2015, 62(9): 2268-2279. https://doi.org/10.1109/TCSI.2015.2459554.
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QIU Y, LIU Y J, ZHOU J, 2018. All-digital blind background calibration technique for any channel time-interleaved adc. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(8): 2503-2514. https://doi.org/10.1109/TCSI.2018.2794529
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Lei Zhao, Zouyi Jiang, Ruoshi Dang, Zhe Cao, Xingshun Gao, Boyu Cheng, Jiadong Hu, Shubin Liu, Qi An. 2018. An 8-Gs/s 12-Bit TIADC System with Real-Time Broadband Mismatch Error Correction. IEEE Transactions on Nuclear Science. 2018, 65(12) :2892-2900. https://doi.org/ 10.1109/TNS.2018.2878875
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H. Shen, D. John and B. Cardiff. 2022. A Background Calibration for Joint Mismatch in the OFDM System with Time-Interleaved ADC. IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3630-3634, https://doi.org/10.1109/TCSII.2022.3182235.
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LIU S, ZHAO L, LI S. 2022. A novel all-digital calibration method for timing mismatch in time interleaved adc based on modulation matrix. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(7): 2955-2967. https://doi.org/10.1109/TCSI.2022.3163431
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H. Shen, A. Blaq, D. John and B. Cardiff. 2023. A Foreground Mismatch and Memory Harmonic Distortion Calibration Algorithm for TIADC, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 3, pp. 1110-1120. https://doi.org/10.1109/TCSI.2022.3229208.
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Chen Xu, Shilie Zheng, Xinyi Chen, Hao Chi, Xiaofeng Jin and Xianmin Zhang. 2015. Photonic-assisted time-interleaved ADC based on optical delay line. Journal of Optics, 2015, 18(1):015704. https://dx.doi.org/10.1088/2040-8978/18/1/015704

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    EITCE '23: Proceedings of the 2023 7th International Conference on Electronic Information Technology and Computer Engineering
    October 2023
    1809 pages
    ISBN:9798400708305
    DOI:10.1145/3650400
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    Published: 17 April 2024

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