skip to main content
research-article

Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+

Published: 08 October 2024 Publication History

Abstract

Advances in quantum computing have posed a future threat to today’s cryptography. With the advent of these quantum computers, security could be compromised. Therefore, the National Institute of Standards and Technology (NIST) has issued a request for proposals to standardize algorithms for post-quantum cryptography (PQC), which is considered difficult to solve for both classical and quantum computers. Among the proposed technologies, the most popular choices are lattice-based (shortest vector problem) and hash-based approaches. Other important categories are public key cryptography (PKE) and digital signatures.
Within the realm of digital signatures lies SPHINCS+. However, there are few implementations of this scheme in hardware architectures. In this article, we present a hardware-software architecture for the SPHINCS+ scheme. We utilized a free RISC-V (Reduced Instruction Set Computer) processor synthesized on a Field Programmable Gate Array (FPGA), primarily integrating two accelerator modules for Keccak-1600 and the Haraka hash function. Additionally, modifications were made to the processor to accommodate the execution of these added modules. Our implementation yielded a 15-fold increase in performance with the SHAKE-256 function and nearly 90-fold improvement when using Haraka, compared to the reference software. Moreover, it is more compact compared to related works. This implementation was realized on a Xilinx FPGA Arty S7: Spartan-7.

References

[1]
Dorian Amiet, Andreas Curiger, and Paul Zbinden. 2018. FPGA-based accelerator for post-quantum signature scheme SPHINCS-256. IACR Transactions on Cryptographic Hardware and Embedded Systems 2018, 1 (2018), 18–39. DOI:
[2]
Dorian Amiet, Lukas Leuenberger, Andreas Curiger, and Paul Zbinden. 2020. FPGA-based SPHINCS + Implementations: Mind the Glitch. In Proceedings of the 2020 23rd Euromicro Conference on Digital System Design. 229–237. DOI:
[3]
Daniel J. Bernstein, Ruben Niederhagen, Andreas Hülsing, Joost Rijneveld, Stefan Kölbl, and Peter Schwabe. 2019. The SpHiNCS+ signature framework. In Proceedings of the ACM Conference on Computer and Communications Security. 2129–2146. DOI:
[4]
Quentin Berthet, Andres Upegui, Laurent Gantel, Alexandre Duc, and Giulia Traverso. 2021. An area-efficient sphincs+post-quantum signature coprocessor. In Proceedings of the 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). 180–187. DOI:
[5]
Johannes Buchmann, Erik Dahmen, and Andreas Hülsing. 2011. XMSS - A practical forward secure signature scheme based on minimal security assumptions. In Proceedings of the Post-Quantum Cryptography: 4th International Workshop, PQCrypto 2011. 117–129. DOI:
[6]
Rafael Calcada. 2022. steel-core. Retrieved from https://github.com/rafaelcalcada/steel-core. Access date: 2022.
[7]
Zhen Zhou, Debiao He, Zhe Liu, Min Luo, and Kim-Kwang Raymond Choo. 2021. A software/hardware co-design of crystals-dilithium signature scheme. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 14, 2 (2021), 1--21.
[8]
Dworkin. 2015. FIPS PUB 202 SHA-3 standard: Permutation-based hash and. NIST Federal Information Processing StandardAugust (2015).
[9]
Pierre-Alain Fouque, Jeffrey Hoffstein, Paul Kirchner, Vadim Lyubashevsky, Thomas Pornin, Thomas Prest, Thomas Ricosset, Gregor Seiler, William Whyte, and Zhenfei Zhang. 2020. Falcon: Fast-fourier lattice-based compact signatures over NTRU specifications v1.2. NIST Post-Quantum Cryptography Standardization Round 3 (2020), 1--65.
[10]
Tim Fritzmann, Georg Sigl, and Johanna Sepulveda. 2020. Extending the RISC-V instruction set for hardware acceleration of the post-quantum scheme LAC. In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. 1420–1425. DOI:
[11]
Tim Fritzmann, Georg Sigl, and Johanna Sepúlveda. 2020. Risq-v: Tightly coupled risc-v accelerators for post-quantum cryptography. IACR Transactions on Cryptographic Hardware and Embedded Systems 2020, 4 (2020), 239–280. DOI:
[12]
Denisa O.C. Greconici, Matthias J. Kannwischer, and Amber Sprenkels. 2021. Compact dilithium implementations on Cortex-M3 and Cortex-M4. IACR Transactions on Cryptographic Hardware and Embedded Systems 2021, 1 (2021), 1–24. DOI:
[13]
ARM Holdings. 2022. ARM architecture reference manual for A-profile architecture. ARM, Cambridge, UK, White Paper (2022).
[14]
Patrick Karl, Jonas Schupp, Tim Fritzmann, and Georg Sigl. 2023. Post-Quantum Signatures on RISC-V with Hardware Acceleration. ACM Transactions on Embedded Computing Systems 1, 1 (2023), 1--23. DOI:
[15]
Stefan Kölbl, Martin M. Lauridsen, Florian Mendel, and Christian Rechberger. 2017. Haraka v2 – efficient short-input hashing for post-quantum applications. IACR Transactions on Symmetric Cryptology 2016, 2 (2017), 1–29. DOI:
[16]
Manish Kumar. 2022. Post-quantum cryptography Algorithm’s standardization and performance analysis. Array 15 (2022), 100242. DOI:
[17]
Ralph C. Merkle. 1990. A certified digital signature. In Proceedings of the Advances in Cryptology — CRYPTO’ 89. Gilles Brassard (Ed.), Springer New York, New York, NY, 218–238.
[18]
NIST. 2016. No Title. Retrieved from https://csrc.nist.gov/projects/post-quantum-cryptography. Access date: 2022.
[19]
Andreas Hülsing, Joost Rijneveld, and Peter Schwabe. 2016. ARMed SPHINCS Computing a 41 KB signature in 16 KB of RAM. Public-Key Cryptography --( PKC'16), Chen-Mou Cheng, Kai-Min Chung, Giuseppe Persiano, and Bo-Yin Yang (Eds.). Springer Berlin Heidelberg, 446--470.
[20]
Deepraj Soni, Kanad Basu, Mohammed Nabeel, Najwa Aaraj, Marcos Manzano, and Ramesh Karri. 2022. Sphincs+ submission to the NIST post-quantum project, v.3.1. Hardware Architectures for Post-Quantum Digital Signature Schemes (2022), 141–162.
[21]
Deepraj Soni, Kanad Basu, Mohammed Nabeel, and Ramesh Karri. 2019. A hardware evaluation study of NIST post-quantum cryptographic signature schemes. (2019), 1–4.
[22]
Jan Philipp Thoma and G. Tim. 2021. A configurable hardware implementation of XMSS. https://eprint.iacr.org/2021/352
[23]
Wen Wang, Bernhard Jungk, Julian Wälde, Shuwen Deng, Naina Gupta, Jakub Szefer, and Ruben Niederhagen. 2020. XMSS and embedded systems: XMSS hardware accelerators for RISC-V. In Proceedings of the International Conference on Selected Areas in Cryptography. 523–550. DOI:
[24]
Wen Wang, Shanquan Tian, Bernhard Jungk, Nina Bindel, Patrick Longa, and Jakub Szefer. 2020. Parameterized hardware accelerators for lattice-based cryptography and their application to the hw/sw co-design of qtesla. IACR Transactions on Cryptographic Hardware and Embedded Systems 2020, 3 (2020), 269–306. DOI:
[25]
A. Waterman and Krste Asanovic. 2019. The RISC-V instruction set manual volume I: Unprivileged ISA - document version 20191213. RISC-V Foundation I (2019). Retrieved from https://riscv.org/technical/specifications/

Cited By

View all
  • (2024)Performance Analysis of Post-Quantum Cryptography Algorithms for Digital SignatureApplied Sciences10.3390/app1412499414:12(4994)Online publication date: 7-Jun-2024
  • (2024)Hardware Design and Security Analysis for SHA-256 in PQC Sphincs+2024 9th International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICICM63644.2024.10814218(93-97)Online publication date: 25-Oct-2024
  • (2024)PESA: Power-Efficient SPHINCS+ Accelerator for Multi-Domain Security Applications on FPGA SoC2024 Twelfth International Symposium on Computing and Networking (CANDAR)10.1109/CANDAR64496.2024.00037(231-237)Online publication date: 26-Nov-2024

Index Terms

  1. Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Transactions on Reconfigurable Technology and Systems
    ACM Transactions on Reconfigurable Technology and Systems  Volume 17, Issue 4
    December 2024
    303 pages
    EISSN:1936-7414
    DOI:10.1145/3613637
    • Editor:
    • Deming Chen
    Issue’s Table of Contents

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 08 October 2024
    Online AM: 27 March 2024
    Accepted: 06 March 2024
    Revised: 17 January 2024
    Received: 19 September 2023
    Published in TRETS Volume 17, Issue 4

    Check for updates

    Author Tags

    1. FPGA
    2. RISC-V
    3. SPHINCS+
    4. hardware-software
    5. processor
    6. post-quantum cryptography

    Qualifiers

    • Research-article

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)549
    • Downloads (Last 6 weeks)69
    Reflects downloads up to 15 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)Performance Analysis of Post-Quantum Cryptography Algorithms for Digital SignatureApplied Sciences10.3390/app1412499414:12(4994)Online publication date: 7-Jun-2024
    • (2024)Hardware Design and Security Analysis for SHA-256 in PQC Sphincs+2024 9th International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICICM63644.2024.10814218(93-97)Online publication date: 25-Oct-2024
    • (2024)PESA: Power-Efficient SPHINCS+ Accelerator for Multi-Domain Security Applications on FPGA SoC2024 Twelfth International Symposium on Computing and Networking (CANDAR)10.1109/CANDAR64496.2024.00037(231-237)Online publication date: 26-Nov-2024

    View Options

    Login options

    Full Access

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Full Text

    View this article in Full Text.

    Full Text

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media