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WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning

Published: 03 May 2024 Publication History

Abstract

To speed up the design closure and improve the QoR of FPGA, supervised single-task machine learning techniques have been used to predict individual design metric based on placement results. However, the design objective is to achieve optimal performance while considering multiple conflicting metrics. The single-task approaches predict each metric in isolation and neglect the potential correlations or dependencies among them. To address the limitations, this article proposes a multi-task learning approach to jointly predict wirelength, congestion and power. By sharing the common feature representations and adopting the joint optimization strategy, the novel WCPNet models (including WCPNet-HS and WCPNet-SS) cannot only predict the three metrics of different scales simultaneously, but also outperform the majority of single-task models in terms of both prediction performance and time cost, which are demonstrated by the results of the cross design experiment. By adopting the cross-stitch structure in the encoder, WCPNet-SS outperforms WCPNet-HS in prediction performance, but WCPNet-HS is faster because of the simpler parameters sharing structure. The significance of the feature imagepinUtilization on predicting power and wirelength are demonstrated by the ablation experiment.

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  1. WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning

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      Published In

      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 29, Issue 3
      May 2024
      374 pages
      EISSN:1557-7309
      DOI:10.1145/3613613
      • Editor:
      • Jiang Hu
      Issue’s Table of Contents

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      Association for Computing Machinery

      New York, NY, United States

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      Publication History

      Published: 03 May 2024
      Online AM: 08 April 2024
      Accepted: 27 March 2024
      Revised: 11 March 2024
      Received: 30 August 2023
      Published in TODAES Volume 29, Issue 3

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      Author Tags

      1. FPGA
      2. physical design
      3. multi-task learning
      4. design metrics prediction

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      • Key-Area Research and Development Program of Guangdong Province under Grant
      • National Natural Science Foundation of China

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