Min Xu
- 1.N. Chang, S. Lin, L. He, O. S. Nakagawa, and W. Xie. Clocktree RLC extraction with efficient inductance modeling. In Design Automation and Test in Europe, March 2000. Google Scholar
Digital Library
- 2.J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali, and S. H.-C. Yen. Analysis and justification of a simple, practical 2 1/2-d capacitance extraction methodology. In Proc. Design Automation Conf, pages 627-632, 1997. Google ScholarDigital Library
- 3.A. Deutsch and et al. When are transmission-line effects important for on-chip wires. IEEE trans on MIT, 1997.Google Scholar
- 4.P. Feldman and R. W. Freund. Reduced-order moldeling of large linear subcircuits via a block lanczos algorithm. In Proc. Design Automation Conf, 1995. Google ScholarDigital Library
- 5.K. Gala, V. Zolotov, R. Panda, B. Young, J. Wang, and D. Blaauw. On-chip inductance modeling and analysis. In Proc. Design Automation Conf, pages 63-68, 2000. Google ScholarDigital Library
- 6.F. W. Grover. Inductance Calculations: working formulas and tables. Dover Publications, 1946.Google Scholar
- 7.L. He, N. Chang, S. Lin, and O. S. Nakagawa. An efficient inductance modeling for on-chip interconnects. In Proc. IEEE Custom Integrated Circuits Conference, pages 457-460, May 1999.Google ScholarCross Ref
- 8.H. Johnson and M. Graham. High-Speed Digital Design - A Handbook of Black Magic. Prentice Hall, 1993. Google ScholarDigital Library
- 9.M. Kamon, S. McCormick, and K. Shepard. Interconnect parasitic extraction in the digital IC design methodology. In Proc. Int. Conf. on Computer Aided Design, 1999. Google ScholarDigital Library
- 10.M. Kamon, M. Tsuk, and J. White. Fasthenry: a multipole-accelerated 3d inductance extraction program. IEEE Trans. on MIT, 1994.Google ScholarCross Ref
- 11.K. M. Lepak, I. Luwandi, and L. He. Simultaneous shield insertion and net ordering for coupled RLC nets under explicit noise constraint. In University of Wisconsin, Technical Report, ECE-00-06, 2000.Google Scholar
- 12.J. Lillis, C. Cheng, S. Lin, and N. Chang. High-performance interconnect analysis and synthesis. John Wiley, to appear in 1999. Google ScholarDigital Library
- 13.A. Odabasioglu, M. Celik, and L. Pileggi. PRIMA: Passive reduced-order interconnect macromodeling algorithm. IEEE trans. on CAD, 1998. Google ScholarDigital Library
- 14.L. Pileggi. Coping with RC(L) interconnect design headaches. In Proc. Int. Conf. on Computer Aided Design, pages 246-253, Nov. 1995. Google ScholarDigital Library
- 15.X. Qi, G. Wang, Z. Yu, and R. W. Dutton. On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation. In Proc. IEEE Custom Integrated Circuits Conference, May 2000.Google Scholar
- 16.A. Ruehli. Inductance calculation in a complex integrated circuit environment. IBM Journal of Res. and Dev., 1972.Google ScholarDigital Library
- 17.A. Ruehli. Equivalent circuit models for three-dimensional multiconductor systems. IEEE Trans. on MIT, 1974.Google Scholar
- 18.Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2000.Google Scholar
- 19.L. Yin and L. He. An efficient analytical model for coupled on-chip RLC interconnects. In Proc. Asia South Pacific Design Automation Conf., January 2001. Google ScholarDigital Library
Index Terms
- An efficient model for frequency-dependent on-chip inductance
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