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F-Bypass: A Low-Power Network-on-Chip Design Utilizing Bypass to Improve Network Connectivity

Published: 28 November 2024 Publication History

Abstract

With the development of transistor feature size to nanometer level, static power consumption has gradually become the main factor affecting the overall power consumption of network-on-chip (NoC). Power gating is an effective technology to reduce static power consumption, but it also brings new challenges, such as BET violation, wake-up latency and network connectivity. Therefore, a power gating method is needed to improve NoC performance and reduce static power consumption. This article proposes a low-power bypass method, namely Forwarding bypass (F-Bypass). First, F-Bypass adds bypass paths between all input and output ports and the network interface (NI) and connects the pop-up port and injection port in NI through the bypass path. When the router is powered off, F-Bypass performs wake-up-free packet transmission, which reduces the break-even time (BET) violation and cumulative wake-up latency while ensuring network connectivity. Secondly, this article adds the modified VC state table to NI so that the power-off router can perform normal traffic control. Finally, a new wake-up criterion is proposed, which can effectively avoid the frequent wake-up of power-off routers, and the detailed hardware implementation of F-Bypass is provided. The simulation results under integrated traffic load show that compared with the traditional scheme, the delay of F-Bypass is reduced by 2.2%, the throughput is increased by 13.1%, and the total static power consumption is reduced by 75.2%. Key performance indicators are superior to other solutions, and the increased area cost is moderate.

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    Published In

    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 20, Issue 4
    October 2024
    89 pages
    EISSN:1550-4840
    DOI:10.1145/3613716
    • Editor:
    • Ramesh Karri
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    Association for Computing Machinery

    New York, NY, United States

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    Publication History

    Published: 28 November 2024
    Online AM: 19 September 2024
    Accepted: 07 September 2024
    Revised: 28 July 2024
    Received: 22 December 2023
    Published in JETC Volume 20, Issue 4

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    Author Tags

    1. Network-on-Chips
    2. Power Gating
    3. Network connectivity
    4. Bypass

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    • National Natural Science Foundation of China (NSFC) research Projects

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