1 Introduction
Systems with high reliability requirements also impose constraints on test overheads, including test data volume, test application time, and design-for-testability (\(DFT\)) logic. The overheads can be reduced if they are shared among different types of tests and optimized together. Sharing and joint optimization of overheads are implemented by the procedure described in this article. The procedure generates a compact transition fault test set with a high fault coverage and low storage requirements supported by \(DFT\) logic under standard scan.
For the discussion in this article, a two-cycle test for transition faults is denoted by \(t_i = \langle s_{i,0} , v_{i,0} ; s_{i,1} , v_{i,1} \rangle\). The state \(s_{i,0}\) is the scan-in state of the test. During the first clock cycle after the scan-in operation of the test, the circuit is in state \(s_{i,0}\) and the primary input vector is \(v_{i,0}\). During the second clock cycle of the test, the circuit is in state \(s_{i,1}\) and the primary input vector is \(v_{i,1}\). The circuit operates in functional mode during the second clock cycle. This implies that the next-state obtained for \(s_{i,1}\) and \(v_{i,1}\) is captured in the flip-flops. The test ends with a scan-out operation.
With enhanced scan [
1], every two-cycle test of the form
\(t_i = \langle s_{i,0} , v_{i,0} ; s_{i,1} , v_{i,1} \rangle\) can be applied. Standard scan allows two types of tests to be applied,
launch-on-capture (\(LOC\)) and
launch-on-shift (\(LOS\)) tests [
2,
3]. During the first clock cycle of an
\(LOC\) test, the circuit operates in functional mode. During the first clock cycle of an
\(LOS\) test, the circuit operates in scan shift mode. This determines
\(s_{i,1}\) to be the next-state of
\(s_{i,0}\) and
\(v_{i,0}\) under an
\(LOC\) test, whereas for an
\(LOS\) test,
\(s_{i,1}\) is obtained by a single shift of
\(s_{i,0}\). Standard scan is assumed here.
Several observations are important for the discussion in this article, which are presented in the next subsections.
1.1 Observation 1
The first observation is that the transition fault coverage is higher if both
\(LOC\) and
\(LOS\) tests are used [
2,
3]. Each type of test detects transition faults that cannot be detected by tests of the other type. Combining the two test types in a single test set allows the highest fault coverage to be achieved under the constraints of standard scan. A static test compaction procedure for a test set that consists of both
\(LOC\) and
\(LOS\) tests was described in [
4].
1.2 Observation 2
The second observation that is important for the discussion in this article is that the insertion of
\(DFT\) logic can increase the transition fault coverage and reduce the number of tests [
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26]. When both
\(LOC\) and
\(LOS\) tests are applied, it is important to share the
\(DFT\) logic between them to avoid increasing the area overhead unnecessarily. An approach that shares
\(DFT\) logic between
\(LOC\) and
\(LOS\) tests is described in this article. The approach is based on the one from [
7]. In the basic approach from [
7], values of selected next-state variables are complemented during the first clock cycles of
\(LOC\) tests. The goal is to change
\(LOC\) tests into enhanced-scan tests and, thus, achieve the transition fault coverage achievable under enhanced scan. Different
\(LOC\) tests may require different subsets of next-state values to be complemented, requiring several control inputs in [
7]. In this article, the
\(DFT\) logic allows next-state values to be complemented during the first clock cycles of both
\(LOC\) and
\(LOS\) tests. A single subset of next-state values that can be complemented is selected. This ensures that a single control input is required for the
\(DFT\) logic. The set of flip-flops with
\(DFT\) logic is denoted by
\(C\). For a circuit with
\(K\) state variables, it is convenient to represent
\(C\) as a vector
\(C = C(0) C(1) ... C(K-1)\), with
\(C(i) = 1\) if flip-flop
\(i\) includes
\(DFT\) logic and
\(C(i) = 0\) if it does not.
1.3 Observation 3
The third observation is related to the test data volume required for applying both
\(LOC\) and
\(LOS\) tests. It was observed in [
27] that input test data can be shared between the two types of tests. Let
\(t_i^{loc} = \langle s_{i,0} , v_{i,0} ; s_{i,1}^{loc} , v_{i,1} \rangle\) be an
\(LOC\) test and let
\(t_i^{los} = \langle s_{i,0} , v_{i,0} ; s_{i,1}^{los} , v_{i,1} \rangle\) be an
\(LOS\) test. The two tests have the same scan-in state and primary input vectors. They differ only in the state obtained during the second clock cycle of the test. This state is determined during test application, and does not need to be stored. To store both tests, it is sufficient to store
\(t_i = \langle s_{i,0} , v_{i,0} , v_{i,1} \rangle\). A vector denoted by
\(A_i\) indicates which tests should be applied to the circuit based on the stored test
\(t_i\). Without
\(DFT\) logic as in [
27], it is possible to consider three options as shown in the first part of Table
1. The test denoted by
\(t_i^0\) is an
\(LOS\) test with the all-0 scan-in vector during the first clock cycle of the test. The all-0 scan-in vector determines the value of the first flip-flop of every scan chain to be 0 during the second clock cycle. The test denoted by
\(t_i^1\) is an
\(LOS\) test with the all-1 scan-in vector during the first clock cycle of the test. Only these two scan-in vectors are considered in [
27]. This is sufficient for allowing the first flip-flop of every scan chain to assume either a 0 or 1 value during the second cycle of an
\(LOS\) test. Although other options for scan-in vectors are possible, only these two options are considered in [
27] and in this article. The test denoted by
\(t_i^2\) is an
\(LOC\) test.
In this article, each of the three tests from the first part of Table
1 can be applied without or with activating the
\(DFT\) logic. Accordingly, there are six entries in
\(A_i\) corresponding to six possible tests as shown in Table
1. For
\(0 \le j \le 5\),
\(A_i(j) = 1\) indicates that the test
\(t_i^j\) is applied to the circuit. Otherwise,
\(A_i(j) = 0\), and
\(t_i^j\) is not applied. With a stored test set denoted by
\(T_{stor}\), the set of tests applied to the circuit is denoted by
\(T_{appl}\) and computed as
\(T_{appl} = \lbrace t_i^j : t_i \in T_{stor} , A_i(j) = 1 \rbrace\). For every value of
\(j\), where
\(0 \le j \le 5\), all the tests for which
\(A_i(j) = 1\) can be applied consecutively, using the same test application process, to avoid switching between test application processes with every test.
1.4 Key Contribution
Based on these observations, the procedure described in this article optimizes four parameters together: (1) the transition fault coverage achieved by \(T_{appl}\), (2) the number of stored tests in \(T_{stor}\), (3) the number of applied tests in \(T_{appl}\), and (4) the size of the \(DFT\) logic described by \(C\). Optimizing the four parameters together is the key contribution of this article.
The procedure accepts a compact test set \(T_{init}\) that consists of \(LOC\) and \(LOS\) tests in which the tests do not share test data. The procedure initializes the \(DFT\) logic by assigning the all-0 vector to \(C\) and creates an initial stored test set \(T_{stor}\) based on \(T_{init}\). It then applies three subprocedures iteratively. Subprocedure 1 adds to \(T_{stor}\) stored tests that are likely to be effective in guiding the insertion of \(DFT\) logic. Subprocedure 2 adjusts the \(DFT\) logic by modifying \(C\) to increase the fault coverage of \(T_{appl}\). Subprocedure 3 compacts \(T_{stor}\) by reconstructing it to take advantage of the updated \(C\). By iterating through the three subprocedures, the procedure ensures that the three components of the solution, namely, the stored test set \(T_{stor}\), the applied test set \(T_{appl}\), and the \(DFT\) logic represented by \(C\), are optimized together. If one component changes, the other components are adjusted in the same or later iterations. The procedure is implemented in an academic environment using academic fault simulation and test generation software tools. Experimental results for benchmark circuits demonstrate the effectiveness of the procedure.
By reducing the number of tests in \(T_{stor}\), the procedure reduces the input test data volume. The number of applied tests in \(T_{appl}\) may increase to support the increase in the fault coverage and the reduction in the number of stored tests. Output compaction is assumed to reduce the output test data volume and allow an increase in the number of applied tests.
A stored test \(t_i = \langle s_{i,0} , v_{i,0} , v_{i,1} \rangle\) can be compressed. In this case, the procedure can consider the compressed test \(t_i\) instead of its entries \(s_{i,0}\), \(v_{i,0}\), and \(v_{i,1}\). In addition, the constraint \(v_{i,0} = v_{i,1}\) can be accommodated by including only one primary input vector in \(t_i\).
The article is organized as follows. Section
2 describes the
\(DFT\) logic that is shared between
\(LOC\) and
\(LOS\) tests. Section
3 describes the iterative test generation and
\(DFT\) insertion procedure. Section
4 presents experimental results for benchmark circuits. Section
5 concludes the article.
2 Shared DFT Logic
This section describes the shared \(DFT\) logic used for increasing the transition fault coverage and reducing the number of tests.
Figure
1 shows a multiplexer-based scan flip-flop. The flip-flop has a present-state variable
\(y_i\) (its output) and a next-state variable
\(Y_i\) (its input during functional operation). The control input of the multiplexer in Figure
1 is the scan enable input
\(s_{en}\). When
\(s_{en} = 0\), the next value of
\(y_i\) is determined by
\(Y_i\). This corresponds to a functional capture cycle. When
\(s_{en} = 1\), the next value of
\(y_i\) is determined by
\(y_{i-1}\). This corresponds to a scan shift cycle. For the first flip-flop of a scan chain,
\(y_{i-1}\) is the scan chain input.
Figure
2 shows the same flip-flop with
\(DFT\) logic for the application of
\(LOC\) tests [
7]. The multiplexer has an additional control input denoted by
\(c_{en}\). A functional capture cycle requires
\(s_{en} c_{en} = 00\). A scan shift cycle requires
\(s_{en} c_{en} = 10\). The
\(DFT\) mode is activated only during the first clock cycle after the scan-in operation of an
\(LOC\) test by assigning
\(s_{en} c_{en} = 01\). In this case, instead of capturing
\(Y_i\), the flip-flop captures the complement
\(\overline{Y_i}\). This allows additional tests to be obtained from
\(LOC\) tests, with complemented present-state values during the second clock cycle.
To share
\(DFT\) logic between
\(LOC\) and
\(LOS\) tests, this article uses the
\(DFT\) logic shown in Figure
3. In addition to the modes of operation of the flip-flop from Figure
2, the flip-flop in Figure
3 has an additional mode with
\(s_{en} c_{en} = 11\). This assignment is made only during the first clock cycle after the scan-in operation of an
\(LOS\) test, which is a scan shift cycle. In this case, instead of capturing
\(y_{i-1}\), the flip-flop captures the complement
\(\overline{y_{i-1}}\). This allows additional tests to be obtained from
\(LOS\) tests, with complemented present-state values during the second clock cycle.
For illustration, let
\(t_i = \langle 00110, 00 , 11 \rangle\) be a stored test for a circuit with a single scan chain that is shifted to the right. Suppose that
\(DFT\) logic is inserted on flip-flop 2, which is replaced by the flip-flop from Figure
3. In this case,
\(C = 00100\). Table
2 shows the
\(LOS\) and
\(LOC\) tests obtained without and with activating the
\(DFT\) logic.
In [
7], the insertion of
\(DFT\) logic was guided by enhanced-scan tests, which detect transition faults that are not detected by
\(LOC\) tests. This requires different flip-flops to operate in
\(DFT\) mode, with
\(s_{en} c_{en} = 01\), under different tests. A subset of flip-flops that operate together in
\(DFT\) mode is referred to as a
\(DFT\) configuration. Each configuration requires its own control input that is connected to all the flip-flops in the same subset. The number of control inputs in [
7] can be high. In this article, a single
\(DFT\) configuration is computed that maximizes the fault coverage using both
\(LOC\) and
\(LOS\) tests. Stored tests based on enhanced-scan tests are added to
\(T_{stor}\) to ensure that they are available for guiding the insertion of
\(DFT\) logic. However, the procedure computes a single set
\(C\) of flip-flops with
\(DFT\) logic, and may not use all the stored tests based on the enhanced-scan tests. Unused tests will be removed from
\(T_{stor}\).
3 Iterative Procedure
This section provides an overview of the iterative test generation and \(DFT\) insertion procedure, and describes its subprocedures.
3.1 Procedure Overview
The procedure accepts a compact test set \(T_{init}\) that consists of \(LOC\) and \(LOS\) tests for transition faults. The tests do not share test data and can be computed by any test generation procedure for transition faults. The set of transition faults is denoted by \(F\).
The procedure represents the \(DFT\) logic by a vector \(C\) as described earlier. Initially, \(C\) is the all-0 vector, and none of the flip-flops includes \(DFT\) logic.
The procedure creates an initial stored test set \(T_{stor}\) based on \(T_{init}\). A test \(t_i \in T_{init}\) is either an \(LOC\) test \(t_i^{loc} = \langle s_{i,0} , v_{i,0} ; s_{i,1}^{loc} , v_{i,1} \rangle\) or an \(LOS\) test \(t_i^{los} = \langle s_{i,0} , v_{i,0} ; s_{i,1}^{los} , v_{i,1} \rangle\). The test \(t_i\) included in \(T_{stor}\) is \(t_i = \langle s_{i,0} , v_{i,0} , v_{i,1} \rangle\). The test \(t_i\) is associated with a vector \(A_i\) that indicates which tests should be applied to the circuit. The set of applied tests is denoted by \(T_{appl}\). The computation of \(T_{appl}\) from \(T_{stor}\) is performed for the initial test set and every time \(T_{stor}\) is updated during the iterative procedure.
The procedure calls three subprocedures iteratively, as shown in Figure
4. It terminates when an iteration does not improve the solution. An improvement occurs when the transition fault coverage is increased, the number of tests in
\(T_{stor}\) is reduced, or the number of tests in
\(T_{appl}\) is reduced.
Subprocedure 1 adds stored tests to \(T_{stor}\) based on enhanced-scan tests that detect transition faults, which are not detected by \(T_{appl}\). The tests are likely to be effective in guiding the insertion of \(DFT\) logic.
Subprocedure 2 adjusts the \(DFT\) logic by modifying \(C\) to increase the fault coverage of \(T_{stor}\). In the first iteration, \(C\) is initially the all-0 vector, and the procedure adds \(DFT\) logic to some of the flip-flops. In later iterations it may remove \(DFT\) logic from some of the flip-flops.
Subprocedure 3 compacts \(T_{stor}\) by reconstructing it to take advantage of the updated \(C\).
By iterating through the three subprocedures, the procedure ensures that \(T_{stor}\), \(T_{appl}\), and \(C\) are optimized together. Whereas the main goal of updating \(C\) is to increase the fault coverage, it also allows \(T_{stor}\) to be compacted. When \(T_{stor}\) is compacted, the number of stored tests is reduced and, in many cases, the fault coverage is increased.
3.2 Computing the Set of Applied Tests
The set of applied tests \(T_{appl}\) is computed based on \(T_{stor}\) as described next. This computation is performed initially and every time \(T_{stor}\) is updated. It involves fault simulation of \(F\) and updating the vectors \(A_i\) associated with the tests in \(T_{stor}\). The goal is to ensure that all the detectable faults in \(F\) are detected using the smallest possible number of applied tests.
Initially,
\(F\) includes all the transition faults, and
\(A_i(j) = 0\) for every test
\(t_i \in T_{stor}\) and every
\(0 \le j \le 5\). Each value of
\(j\) corresponds to a test
\(t_i^j\) as shown in Table
1. For a fault
\(f \in F\),
\(i_{det}(f) = -1\) and
\(j_{det}(f) = -1\) initially. These values will be updated when
\(f\) is detected.
For every test \(t_i \in T_{stor}\) and every \(0 \le j \le 5\), the procedure performs fault simulation with fault dropping of \(F\) under \(t_i^j\). If a fault \(f \in F\) is detected by \(t_i^j\), the procedure assigns \(i_{det}(f) = i\) and \(j_{det}(f) = j\). If any faults are detected by \(t_i^j\), the procedure assigns \(A_i(j) = 1\).
Next, the procedure attempts to eliminate the need for some of the applied tests. For this purpose, it considers every test \(t_i^j\) such that \(A_i(j) = 1\). To check whether the assignment \(A_i(j) = 0\) is acceptable, the procedure considers every fault \(f \in F\) with \(i_{det}(f) = i\) and \(j_{det}(f) = j\). The set of target faults is denoted by \(F_{i,j} = \lbrace f \in F : i_{det}(f) = i , j_{det}(f) = j \rbrace\). The procedure simulates \(F_{i,j}\) under every test \(t_p^{r}\) such that \(A_p(r) = 1\), and either \(p \ne i\) or \(r \ne j\). If a fault \(f \in F_{i,j}\) is detected by \(t_p^{r}\), the procedure assigns \(i_{det}(f) = p\) and \(j_{det}(f) = r\). If no fault remains for which \(i_{det}(f) = i\) and \(j_{det}(f) = j\), the procedure assigns \(A_i(j) = 0\).
3.3 Subprocedure 1 — Adding Stored Tests
The goal of subprocedure 1 is to add tests to \(T_{stor}\) that are likely to be effective in guiding the insertion of \(DFT\) logic. A stored test \(t_i\) added to \(T_{stor}\) by subprocedure 1 is not expected to produce a test \(t_i^j\), with \(0 \le j \le 5\), that increases the fault coverage. However, subprocedure 2 may adjust set \(C\) to ensure that \(t_i\) increases the fault coverage.
Subprocedure 1 uses a stuck-at test set \(W\) to compute enhanced-scan tests. A test \(w_a \in W\) has the form \(w_a = \langle s_a , v_a \rangle\), where \(s_a\) is a scan-in state, and \(v_a\) is a primary input vector. For every pair of tests \(w_a \in W\) and \(w_b \in W\), the procedure constructs a two-cycle test \(w_{a,b} = \langle s_a , v_a ; s_b , v_b \rangle\). The test may not be an \(LOC\) or \(LOS\) test. Its importance is two-fold, as discussed next.
To detect a transition fault \(f \in F\), the first cycle of the test must activate a stuck-at fault on the same line (a stuck-at 1 fault for a \(0 \rightarrow 1\) transition fault and a stuck-at 0 fault for a \(1 \rightarrow 0\) transition fault). In addition, the second cycle of the test must detect the opposite stuck-at fault on the same line (a stuck-at 0 fault for a \(0 \rightarrow 1\) transition fault and a stuck-at 1 fault for a \(1 \rightarrow 0\) transition fault). If the stuck-at fault is undetectable, the corresponding transition fault is undetectable. Two-cycle tests that combine stuck-at tests thus provide information about the transition faults that are expected to be detectable. The set \(F_{enh} \subseteq F\) consists of transition faults for which two-cycle tests based on \(W\) exist. Such faults are expected to be detectable using \(LOC\) and \(LOS\) tests with \(DFT\) logic based on the next point.
If a test \(w_{a,b} = \langle s_a , v_a ; s_b , v_b \rangle\) detects a transition fault \(f\), the stored test and \(DFT\) logic required for detecting \(f\) can be computed as follows. The stored test is \(t_i = \langle s_a , v_a , v_b \rangle\). For \(0 \le j \le 5\), let \(t_i^j = \langle s_a , v_a ; s_b^j , v_b \rangle\), where \(s_a\), \(v_a\), and \(v_b\) are determined by \(t_i\) and \(s_b^j\) is the state of the circuit in the second cycle of the test, which depends on the test type given by \(j\). For \(0 \le j \le 2\), the \(DFT\) logic needs to modify \(s_b^j\) into \(s_b^{j+3} = s_b\) by complementing the bits where \(s_b^j\) and \(s_b\) differ.
For example, suppose that
\(w_a = \langle 00110 , 00 \rangle\) and
\(w_b = \langle 10111 , 11 \rangle\). This yields
\(w_{a,b} =\) \(\langle 00110, 00 ;\) \(10111 , 11 \rangle\). Suppose that
\(w_{a,b}\) detects a transition fault
\(f\). However, it is not an
\(LOC\) or
\(LOS\) test. It is possible to define an
\(LOS\) test
\(t_i^4 = w_{a,b}\) by using
\(t_i = \langle 00110, 00 , 11 \rangle\) and
\(C = 00100\). Table
2 shows the tests that can be applied based on
\(t_i\) and
\(C\). In this case,
\(t_i^1 = \langle 00110, 00 ; 10011 , 11 \rangle\), and
\(t_i^4 = \langle 00110, 00 ; 10111 , 11 \rangle\) that detects
\(f\).
Based on this discussion, subprocedure 1 adds to \(T_{stor}\) the test \(t_i = \langle s_a , v_a , v_b \rangle\) for every pair of tests \(w_a \in W\) and \(w_b \in W\) such that \(w_{a,b} = \langle s_a , v_a ; s_b , v_b \rangle\) detects a transition fault, which is not already detected by \(T_{stor}\).
3.4 Subprocedure 2 — DFT Insertion
For a circuit with
\(K\) state variables,
\(C = C(0)\) \(C(1)\) ...
\(C(K-1)\), where
\(C(i) = 0\) if flip-flop
\(i\) is as shown in Figure
1 and
\(C(i) = 1\) if flip-flop
\(i\) is as shown in Figure
3. Initially,
\(C(i) = 0\) for
\(0 \le i \lt K\). In an arbitrary iteration,
\(C(i)\) may be 0 or 1.
Subprocedure 2 updates \(C\) in every iteration with the goal of ensuring that \(C\) is matched to \(T_{stor}\) considering the entire set of target faults \(F\). To obtain a single \(DFT\) configuration, represented by \(C\), it is not possible to consider faults from \(F\) or tests from \(T_{stor}\) one by one. The entire sets \(T_{stor}\) and \(F\) need to be considered together.
The matching of \(C\) to \(T_{stor}\) is performed by complementing bits of \(C\) one by one and checking the effect on the fault coverage of \(T_{stor}\). Instead of considering all the bits of \(C\), it is possible to focus on flip-flops in logic cones of undetected faults from \(F\) and on flip-flops that already have \(DFT\) logic.
Updating \(C\) in an iteration is partitioned into two phases. The goal of the first phase is to increase the fault coverage as much as possible. The goal of the second phase is to ensure that as few flip-flops as possible require \(DFT\) logic. Each phase performs several passes over all the flip-flops in a random order. Additional passes are performed as long as the fault coverage increases. In the second phase, additional passes are also performed as long as the number of flip-flops with \(DFT\) logic decreases.
When flip-flop
\(i\) is considered, the procedure complements
\(C(i)\), thus changing the type of the flip-flop between Figures
1 and
3. With the updated status of flip-flop
\(i\), the procedure checks whether all the faults detected earlier continue to be detected. If so, the procedure checks whether additional faults are detected. If additional faults are detected, the complemented value of
\(C(i)\) is accepted regardless of the phase. If fewer faults are detected, the complemented value of
\(C(i)\) is not accepted and
\(C(i)\) is complemented again. The remaining conditions depend on the phase. In the first phase, complementation of
\(C(i)\) is accepted if all the faults detected earlier continue to be detected, even if no new faults are detected. This is important for allowing other changes in
\(C\) to increase the fault coverage. In the second phase, the procedure also requires that
\(C(i) = 0\). Thus, the second phase does not allow
\(C(i) = 1\) to be retained if no new faults were detected. This is important for reducing the number of flip-flops with
\(DFT\) logic.
3.5 Subprocedure 3 — Test Compaction
Subprocedure 3 modifies the set \(T_{stor}\) to match it to \(C\). The main goal of subprocedure 3 is to reduce the number of tests in \(T_{stor}\). By matching \(T_{stor}\) to \(C\) subprocedure 3 also identifies opportunities to detect additional faults. Experimental results indicate that after the first iteration, most of the increase in the fault coverage is achieved when \(T_{stor}\) is matched to \(C\). Updating of \(C\) is important for allowing \(T_{stor}\) to be modified further.
To compact \(T_{stor}\), subprocedure 3 initially assigns \(T_{prev} = T_{stor}\) and \(T_{stor} = \emptyset\). The procedure reconstructs \(T_{stor}\) by considering the tests from \(T_{prev}\) one by one. The set of target faults \(F\) initially includes all the transition faults.
When a test \(t_i \in T_{prev}\) is considered, the procedure applies the following steps. The procedure first finds the subset of tests \(T_i = \lbrace t_i^0 , t_i^1 , ... , t_i^5 \rbrace\) based on \(t_i\). It simulates \(F\) under \(T_i\) to find the subset of detected faults \(F_i \subseteq F\). If \(F_i = \emptyset\), the test \(t_i\) is not considered further. Otherwise, the procedure will add \(t_i\) to \(T_{stor}\), and remove the faults in \(F_i\) from \(F\).
Before making these changes, the procedure attempts to modify \(t_i\) to increase the subset of faults detected by \(T_i\). The modification of \(t_i\) is achieved by complementing its bits one by one in a random order. The complementation of a bit is accepted if all the faults in \(F_i\) continue to be detected by \(T_i\). If new faults are detected, they are added to \(F_i\).
The procedure considers all the bits of \(t_i\) repeatedly until a pass over all the bits does not add new faults to \(F_i\).
3.6 Example
Table
3 shows an example of the procedure based on benchmark
\(s298\). The initial test set
\(T_{stor}\) with the all-0 vector
\(C\) is described in the first row. Additional rows describe the solution obtained after every subprocedure is applied in every iteration, until the procedure terminates. Column
\(iter\) shows the iteration, and column
\(subp\) shows the subprocedure. Column
\(dft\) shows the vector
\(C\). Column
\(stor\) shows the number of tests in
\(T_{stor}\), and column
\(appl\) shows the number of tests in
\(T_{appl}\). Column
\(f.c.\) shows the transition fault coverage. Column
\(gap\) shows the percentage of undetected faults that can be detected by enhanced-scan tests. This percentage is based on the set
\(F_{enh}\) computed earlier and referred to as the fault coverage gap.
Considering the first iteration, subprocedure 1 adds to \(T_{stor}\) 18 tests that may be used for guiding the insertion of \(DFT\) logic. Subprocedure 2 inserts \(DFT\) logic on five flip-flops, increasing the transition fault coverage to 99.832% and reducing the gap to 0.168%. Subprocedure 3 reduces the number of stored tests to 26 and decreases the gap to zero.
In the second iteration, subprocedure 1 does not add any tests to \(T_{stor}\). Subprocedure 2 reduces the number of flip-flops with \(DFT\) logic to four. The procedure terminates with 25 tests in \(T_{stor}\).
The number of applied tests in the initial test set is 36 instead of 35. The number of applied tests increases to 45 to allow the fault coverage to increase and the number of stored tests to decrease.
4 Experimental Results
The results of the iterative test generation and \(DFT\) insertion procedure are presented in this section.
The results are shown in Tables
4 and
5. There are up to three rows for every circuit in Tables
4 and
5. The first row describes the initial test set
\(T_{stor}\) obtained from the compact
\(LOC\) and
\(LOS\) test set
\(T_{init}\) with no
\(DFT\) logic. The second row describes the results obtained after the first iteration of the procedure. The last row describes the final result.
For each case, after the name of the circuit, column \(sv\) shows the number of state variables (flip-flops), and column \(pi\) shows the number of primary inputs. Column \(iter\) shows the iteration of the procedure. Column \(dft\) shows the number of flip-flops with \(DFT\) logic. Column \(stor\) shows the number of tests in \(T_{stor}\). Column \(frac\) that follows shows the ratio of the number of tests in \(T_{stor}\) to the number of tests in \(T_{init}\). Column \(appl\) shows the number of tests in \(T_{appl}\). Column \(frac\) that follows shows the ratio of the number of tests in \(T_{appl}\) to the number of tests in \(T_{init}\). Column \(f.c.\) shows the transition fault coverage. Column \(gap\) shows the percentage of undetected faults that can be detected by enhanced-scan tests. The circuits are ordered from high to low gap considering the initial test set. Column \(ntime\) shows the normalized runtime, which is the total runtime divided by the runtime for fault simulation of the initial test set \(T_{stor}\). The normalized runtime provides an indication of the computational effort in terms of fault simulation time.
The following points can be seen from Tables
4 and
5. The test generation and
\(DFT\) insertion procedure has two main objectives: increasing the transition fault coverage and reducing the number of stored tests. By reducing the number of stored tests, the procedure reduces the storage requirements.
The effect of the procedure on the fault coverage can be seen from columns \(f.c.\) and \(gap\). The use of both \(LOC\) and \(LOS\) tests provides a high initial fault coverage. The test generation and \(DFT\) insertion procedure increases the transition fault coverage further and reduces the gap over multiple iterations. In several cases, the gap is reduced to zero.
The number of flip-flops with \(DFT\) logic is shown under column \(dft\). For most of the circuits considered, fewer than 10% of the flip-flops require \(DFT\) logic. Additional iterations sometimes allow the procedure to reduce the number of flip-flops with \(DFT\) logic. This occurs even when the fault coverage is increased.
Considering the number of stored tests, it is reduced significantly for all the circuits considered. The number of applied tests is increased relative to the number of tests in \(T_{init}\) to support the increase in fault coverage and the reduction in the number of stored tests.
The normalized runtime does not increase with the size of the circuit, and larger circuits sometimes have lower normalized runtimes. This indicates that the procedure scales similar to a fault simulation procedure.
Bounds on the percentage of flip-flops with \(DFT\) logic and the percentage increase in the number of applied tests can be incorporated into the procedure. Such bounds were not used in this article to show the full potential of the procedure in increasing the transition fault coverage and reducing the number of stored tests.