Abstract
An interesting property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as long as it can "borrow" time from the shorter paths in the subsequent logic stages. This gives designers a lot of flexibility in designing circuits, especially high performance ones. However, it also increases the complexity in timing analysis. Finding the best clock period or determining how much time to borrow from the subsequent logic stages is difficult especially for designs containing multiple clocks, mixed-clock paths, user-specified multicycle paths, and false paths. In this article, we formulate the time borrowing problem as a linear programming problem. An optimal time borrowing solution can be found by solving the formulation. Based on this time borrowing solver, algorithms are proposed for timing optimization to achieve the optimal clock period. Experimental results show our algorithm is efficient and yields very good results.
- BELKHALE, K. AND SUESS, A. 1995. Timing analysis with known false subgraphs. In Proceedings of IEEE/ACM ICCAD (Nov.), 736-740. Google Scholar
- LEE, J., TANG, D., AND WONG, C. 1994. A timing analysis algorithm for circuits with level-sensitive latches. In Proceedings of IEEE/ACM ICCAD (Nov.), 743-748. Google Scholar
- SAKALLAH, K., MUDGE, T., AND OLUKOTUN, O. 1990a. Analysis and design of latch-controlled synchronous digital circuits. In Proceedings of ACM/IEEE DAC (June), 111-117. Google Scholar
- SAKALLAH, K., MUDGE, T., AND OLUKOTUN, O. 1990b. Check tc and min tc: Timing verification and optimal clocking of synchronous digital circuit. In Proceedings of IEEE/ACM ICCAD (Nov.), 552-555.Google Scholar
- SZYMANSKI, T. 1992. Computing optimal clock schedules. In Proceedings of ACM/IEEE DAC (June), 399-404. Google Scholar
- SZYMANSKI, T. AND SHENOY, N. 1992. Verifying clock schedules. In Proceedings of IEEE/ACM ICCAD (Nov.), 124-131. Google Scholar
Index Terms
- Optimal time borrowing analysis and timing budgeting optimization for latch-based designs
Recommendations
Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits
ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided DesignPulsed-latches take advantage of both latches in their high performance and flip-flops in their convenience of timing analysis. To minimize the clock period of pulsed-latch-based circuits for a higher performance, a problem of combined retiming and time ...
Latch-Based Performance Optimization for FPGAs
FPL '11: Proceedings of the 2011 21st International Conference on Field Programmable Logic and ApplicationsWe explore using pulsed latches for timing optimization -- a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle. We exploit existing functionality within commercial FPGA chips ...
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits
This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is ...
Comments