ABSTRACT
This paper proposes a reconfigurable processing unit, which performs the MPEG-4 repetitive padding algorithm in real time. The padding unit has been implemented as a scalable systolic structure of processing elements. A generic array of PE has been described in VHDL, and the functionality of the unit has been validated by simulations. In order to determine the chip area and speed of the padding structure, we have synthesized the structure for two FPGA families - Xilinx and Altera. The simulation results indicate that the proposed padding unit can operate in a wide frequency range, depending on the implemented configuration. It is shown that it can process from tens up to hundreds of thousands MPEG-4 macroblocks per second. This allows the real-time requirements of all MPEG-4 profiles and levels to be met efficiently at trivial hardware costs. Finally, the trade-off between chip-area and operating speed is discussed and possible configuration alternatives are proposed.
- 1.ALTERA. Data Book. Altera Corp., 1998.]]Google Scholar
- 2.M. Berekovic, H.-J. Stolberg, M. B. Kulaczewski, P. Pirsh, H. Moler, H. Runge, J. Kneip, and B. Stabernack. Instruction set extensions for mpeg-4 video. Journal of VLSI Signal Processing, 23(1):27-49, October 1999.]]Google ScholarDigital Library
- 3.H.-C. Chang, L.-G. Chen, M.-Y. Hsu, and Y.-C. Chang. Performance analysis and architecture evaluation of MPEG-4 video codec system. In IEEE International Symposium on Circuits and Systems, volume II, pages 449-452, Geneva, Switzerland, 28-31 May 2000.]]Google Scholar
- 4.E. A. Edirisinghe, J. Jiang, and C. Grecos. Shape adaptive padding for MPEG-4. IEEE Transactions on Consumer Electronics, 46(3):514-520, August 2000.]]Google ScholarDigital Library
- 5.C. Heer and K. Migge. VLSI hardware accelerator for the MPEG-4 padding algorithm. In IS&T:SPIE Conference on media processors, volume 3655, pages 113-119, 1999.]]Google Scholar
- 6.ISO/IEC JTC11/SC29/WG11 N2802. ISO/IEC 14496-2. Generic Coding of Audio-visual Objects- Part2: Visual. Final Proposed Draft, July 1999.]]Google Scholar
- 7.ISO/IEC JTC11/SC29/WG11, N3312. MPEG-4 video verification model version 16.0.]]Google Scholar
- 8.ISO/IEC JTC11/SC29/WG11 N4030. MPEG-4 overview, March 2001.]]Google Scholar
- 9.A. Kaup. Object-based texture coding of moving video in MPEG-4. IEEE Transactions on Circuits and Systems for Video Technology, 9(1):5-15, February 1999.]]Google ScholarDigital Library
- 10.J. Kneip, S. Bauer, J. Vollmer, B. Schmale, P. Kuhn, and M. Reissmann. The MPEG-4 video coding standard - a VLSI point of view. In IEEE Workshop on Signal Processing Systems,(SIPS98), pages 43-52, 8-10 Oct. 1998.]]Google ScholarCross Ref
- 11.J.-H. Moon, J.-H. Kweon, and H.-K. Kim. Boundary block-merging (BBM) technique for efficient texture coding of arbitrarily shaped object. IEEE Transactions on Circuits and Systems for Video Technology, 9(1):35-43, February 1999.]]Google ScholarDigital Library
- 12.Y. Q. Shi and H. Sun. Image and Video Compression for Multimedia Engineering. Boca Raton CRC Press, 2000.]] Google ScholarDigital Library
- 13.H.-J. Stolberg, M. Berekovic, P. Pirsch, H. Runge, H. Moller, and J. Kneip. The M-PIRE MPEG-4 codec DSP and its macroblock engine. In IEEE International Symposium on Circuits and Systems, volume II, pages 192-195, Geneva, Switzerland, 28-31 May 2000.]]Google Scholar
- 14.S. Vassiliadis, G. Kuzmanov, and S. Wong. MPEG-4 and the New Multimedia Architectural Challenges. In 15th International Conference SAER'2001, St.Konstantin, Bulgaria, 21-23 Sept. 2001.]]Google Scholar
- 15.S. Vassiliadis, S. Wong, and S. Cotofana. The MOLEN rm-coded processor. In 11th International Conference on Field Programmable Logic and Applications (FPL), Belfast, Northern Ireland, UK, August 2001.]] Google ScholarDigital Library
- 16.XILINX. DataSource CD-ROM. XILINX, 2000.]]Google Scholar
Index Terms
- Reconfigurable repetitive padding unit
Recommendations
Hardwired MPEG-4 repetitive padding
We consider two hardwired solutions for repetitive padding, a performance restricting algorithm for real time MPEG-4 execution. The first solution regards application specific implementations, the second regards general purpose processing. For the ...
A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit
CIT '10: Proceedings of the 2010 10th IEEE International Conference on Computer and Information TechnologyIt’s a promising way to improve performance significantly by adding reconfigurable processing unit to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is ...
Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures
Dynamically reconfigurable architectures, such as NATURE, achieve high logic density and low reconfiguration latency compared to traditional field-programmable gate arrays. Unlike fine-grained NATURE, reconfigurable DSP block incorporated NATURE ...
Comments