ABSTRACT
Cycle time models perform an a-priori calculation of local signal delays by estimating the lengths of wires connecting different levels of synchronously clocked logic elements. Typically, a signal will have to pass through approximately 15-25 layers of logic during a single clock cycle and it is has been assumed that this number is sufficiently large to allow average wire lengths to be used. This paper investigates the accuracy of this mean value assumption by comparing cycle times calculating using average wire lengths with cycle times calculated using wires sampled from an estimate of the wire length distribution in each wiring layer. The sampling algorithm provides a more accurate calculation of the cycle time and also an estimate of its variation due to the inherently stochastic nature of the layout process. Results for a benchmark netlist, implemented in 0.25 μm technology, indicate that for a logic depth of 25 the mean value assumption is satisfactory and that clock rate has a standard deviation of approximately 5% of this mean value due to the inherently stochastic nature of the layout process.
- 1.H. B. Bakoglu and J. D. Meindl, "A system-level circuit model for multi- and single-chip CPU's," in Proc. IEEE ISSCC. 1987, pp. 308-309, ACM/SIGDA Press.Google Scholar
- 2.B. Geuskens, Modeling the influence of multilevel interconnect on chip performance, Ph.D. thesis, Rensselaer Polytechnic Institute, Troy, New York, June 1997. Google ScholarDigital Library
- 3.J. C. Eble, V. K. De, D. S. Wills, and J. D. Meindl, "A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001," in Proc. IEEE Intl. ASIC Conf., September 1996, pp. 193-196.Google Scholar
- 4.D. Sylvester and K. Keutzer, "System-level performance modeling with BACPAC - Berkeley advanced chip performance calculator," in IEEE/ACM Intl. Workshop on System-Level Interconnect Prediction, April 1999, pp. 109-114.Google Scholar
- 5.T. N. Theis, "The future of interconnection technology," IBM J. Research and Development, vol. 44, no. 3, pp. 379-389, May 2000. Google ScholarDigital Library
- 6.R. A. Wildman, J. I. Kramer, D. S. Weile, and P. Christie, "Wire layer geometry optimization using stochastic wire sampling," in Submitted to the 4th IEEE/ACM Intl. Workshop on System Level Interconnect Prediction (SLIP), 2002. Google ScholarDigital Library
- 7.T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and cross-talk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp. 118-184, 1993.Google ScholarCross Ref
- 8.Phillip Christie and Dirk Stroobandt, "The interpretation and application of rent's rule," IEEE Trans. on VLSI Systems, pp. 639-648, December 2000. Google ScholarDigital Library
- 9.W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical recipes in C, Cambridge University Press, Cambridge, UK, 1988.Google ScholarDigital Library
- 10.Eric Nequist and Lou Scheffer, "Why interconnect prediction doesn't work," in Proceddings 2nd International Workshop on System Level Interconnect Prediction. April 2000, pp. 139-144, ACM Press. Google ScholarDigital Library
Index Terms
- Stochastic wire length sampling for cycle time estimation
Recommendations
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rates. Based on binary trees, the MP-tree is very efficient, effective, and ...
X-architecture placement based on effective wire models
ISPD '07: Proceedings of the 2007 international symposium on Physical designIn this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture placement, including the Manhattan-half-perimeter wirelength (MHPWL) model, the ...
Effective Wire Models for X-Architecture Placement
In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture placement, including the Manhattan-half-perimeter wirelength (MHPWL) model, the ...
Comments