Faran Rafiq
ABSTRACT
A new approach to the interconnect-driven floorplanning problem that integrates bus planning with floorplanning is presented. The integrated floorplanner is intended for bus-based designs. Each bus consists of a large number of wires. The floorplanner ensures routability by generating the exact location and shape of interconnects (above and between the circuit blocks) and optimizes the timing. Experiments with MCNC benchmarks clearly show the superiority of integrated floorplanning over the classical floorplan-analyze-and-then-re-floorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12-13% smaller in area as compared to the traditional floorplanning algorithms.
- H. Chen, H. Zhou, F.Y. Young, D.F. Wong, H. Yang, and N. Sherwani, "Integrated Floorplanning and Interconnect Planning", IEEE International Conference on CAD, 1999. Google Scholar
Digital Library
- T. Chen and M. K. H. Fan, "On Convex Formulation of the Floorplan Area Minimization Problem", International Symposium on Physical Design, pp. 124--128, April 1998. Google ScholarDigital Library
- T. S. Moh, T.S. Chang, and S. L. Hakimi, "Globally Optimal Floorplanning for a Layout Problem", IEEE Transactions on Circuits and Systems: Fundamental Theory and Applications, Vol. 43, pp. 713--720, Sep 1996.Google ScholarCross Ref
- H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectangle-packing-Based Module Placement", Proc. of International Conference on CAD, pp. 472--479, 1995. Google ScholarDigital Library
- S. Nakatake, K. Sakanushi, Y. Kajitani and M. Kawatika, "The Channeled BSG: A universal floorplanner for Simultaneous Place/Route with IC applications", Proc. IEEE International Conference on CAD, pp.418--425, 1998. Google ScholarDigital Library
- R. H. J. M. Otten, "Efficient Floorplan Optimization," IEEE International Conference on CAD, pp. 499--502, 1983.Google Scholar
- Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer Academic Publishers, 1998. Google ScholarDigital Library
- Peichan Pan and C. L. Liu, "Area Minimization of General Floorplans", Proc. of International Conference on Computer Aided Design, pp 606--609, 1992. Google ScholarDigital Library
- P. Pan and C. L. Liu, "Area Minimization for general floorplans," Proc. IEEE International Conference on Computer Aided Design, pp. 606--609, 1993. Google ScholarDigital Library
- D.F. Wong and C. L. Liu, "A new Algorithm for Floorplan Design," Proc. of the Design Automation Conference, 1986. Google ScholarDigital Library
- N. P. Guo, C-K Chen and T. Yoshimura, "An O-tree representation of non-slicing floorplan and its application," Proc.of DAC, pp. 268--273, June 1999. Google ScholarDigital Library
- M. Chrzanowska-Jeske, G. Greenwood, B. Wang, "Combing Evolution Strategies with Lagrangian Relaxation for Constructing Non-slicing VLSI Floorplans with Soft Modules," Congress on Evolutionary Computing, 2002. Google ScholarDigital Library
Index Terms
- Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
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