Jiang Hu
Charles J. Alpert
ABSTRACT
Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several existing buffer insertion algorithms have evolved from van Ginneken's classic algorithm. In this work, we extend van Ginneken's algorithm to handle blockages in the layout. Given a Steiner tree containing a Steiner point that overlaps a blockage, a local adjustment is made to the tree topology that enables additional buffer insertion candidates to be considered. This adjustment is adaptive to the demand on buffer insertion and is incurred only when it facilitates the maximal slack solution. This approach can be combined with any performance-driven Steiner tree construction. The overall time complexity has linear dependence on the number of blockages and quadratic dependence on the number of potential buffer locations. Experiments on several large nets confirm that high-quality solutions can be obtained through this technique with little CPU cost.
- C. Alpert, G. Gandham, M. Hrkic, J. Hu, A. Kahng, J. Lillis, B. Liu, S. Quay, S. Sapatnekar, A. Sullivan, and P. Villarrubia. Buffered Steiner trees for difficult instances. In ISPD, pages 4--9, 2001. Google Scholar
Digital Library
- C. J. Alpert and A. Devgan. Wire segmenting for improved buffer insertion. In DAC, pages 588--593, 1997. Google ScholarDigital Library
- C. J. Alpert, A. Devgan, and S. T. Quay. Buffer insertion with accurate gate and interconnect delay computation. In DAC, pages 479--484, 1999. Google ScholarDigital Library
- C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay, and S. S. Sapatnekar. A Steiner tree construction for buffers, blockages, and bays. IEEE Transactions on CAD, 20(4):556--562, Apr. 2001. Google ScholarDigital Library
- J. Cong. Challenges and opportunities for design innovations in nanometer technologies. SRC Design Sciences Concept Paper, 1997.Google Scholar
- J. Cong, T. Kong, and D. Z. Pan. Buffer block planning for interconnect-driven floorplanning. In ICCAD, pages 358--363, 1999. Google ScholarDigital Library
- J. Cong and X. Yuan. Routing tree construction under fixed buffer locations. In DAC, pages 379--384, 2000. Google ScholarDigital Library
- M. de Berg, M. van Kreveld, M. Overmars, and O. Schwarzkopf. Computational geometry: algorithms and applications. Springer-Verlag, 1997. Google ScholarDigital Library
- W. C. Elmore. The transient response of damped linear networks with particular regard to wideband amplifiers. Journal of Applied Physics, 19:55--63, Jan. 1948.Google ScholarCross Ref
- M. Hanan. On Steiner's problem with rectilinear distance. SIAM Journal on Applied Mathematics, 14(2):255--265, 1966.Google ScholarCross Ref
- A. Jagannathan, S.-W. Hur, and J. Lillis. A fast algorithm for context-aware buffer insertion. In DAC, pages 368--373, 2000. Google ScholarDigital Library
- M. Lai and D. Wong. Maze routing with buffer insertion and wiresizing. In DAC, pages 374--378, 2000. Google ScholarDigital Library
- J. Lillis, C. K. Cheng, T. T. Lin, and C. Y. Ho. New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing. In DAC, pages 395--400, 1996. Google ScholarDigital Library
- J. Lillis, C. K. Cheng, and T. T. Lin. Optimal wire sizing and buffer insertion for low and a generalized delay model. IEEE Journal of Solid-State Circuits, 31(3):437--447, Mar. 1996.Google ScholarCross Ref
- J. Lillis, C. K. Cheng, and T. T. Lin. Simultaneous routing and buffer insertion for high performance interconnect. In Proceedings of the Great Lake Symposium on VLSI, pages 148--153, 1996. Google ScholarDigital Library
- T. Okamoto and J. Cong. Interconnect layout optimization by simultaneous Steiner tree construction and buffer insertion. In ACM Physical Design Workshop, pages 1--6, 1996.Google Scholar
- A. H. Salek, J. Lou, and M. Pedram. A simultaneous routing tree construction and fanout optimization algorithm. In ICCAD, pages 625--630, 1998. Google ScholarDigital Library
- A. H. Salek, J. Lou, and M. Pedram. MERLIN: Semi-order-independent hierarchical buffered routing tree generation using local neighborhood search. In DAC, pages 472--478, 1999. Google ScholarDigital Library
- X. Tang, R. Tian, H. Xiang, and D. Wong. A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints. In ICCAD, pages 49--56, 2001. Google ScholarDigital Library
- L. P. P. P. van Ginneken. Buffer placement in distributed RC-tree networks for minimal elmore delay. In ISCAS, pages 865--868, 1990.Google ScholarCross Ref
- H. Zhou, D. F. Wong, I.-M. Liu, and A. Aziz. Simultaneous routing and buffer insertion with restrictions on buffer locations. In DAC, pages 96--99, 1999. Google ScholarDigital Library
Index Terms
- Buffer insertion with adaptive blockage avoidance
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