Christoph Kessler
ABSTRACT
In contrast to standard compilers, generating code for DSPs can afford spending considerable resources in time and space on optimizations. Generating efficient code for irregular architectures requires an integrated method that optimizes simultaneously for instruction selection, instruction scheduling, and register allocation.We describe a method for fully integrated optimal code generation based on dynamic programming. We introduce the concept of residence classes and space profiles, which allows us to describe and optimize for irregular register and memory structures. In order to obtain a retargetable framework we introduce a structured architecture description language, ADML, which is based on XML. We implemented a prototype of such a retargetable system for optimal code generation. Results for variants of the TI C62x show that our method can produce optimal solutions to small but nontrivial problem instances with a reasonable amount of time and space.
- A. Aho and S. Johnson. Optimal Code Generation for Expression Trees. J. ACM, 23(3): 488--501, July 1976.]] Google Scholar
Digital Library
- H.-C. Chou and C.-P. Chung. An Optimal Instruction Scheduler for Superscalar Processors. IEEE Transactions on Parallel and Distributed Systems, 6(3): 303--313, 1995.]] Google ScholarDigital Library
- C. W. Fraser and D. R. Hanson. A Retargetable C Compiler: Design and Implementation. Benjamin Cummings Publishing Co., 1995.]] Google ScholarDigital Library
- R. Freiburghouse. Register Allocation via Usage Counts. Comm. ACM, 17(11), 1974.]] Google ScholarDigital Library
- S. Hanono and S. Devadas. Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Design Automation Conference, pages 510--515, 1998.]] Google ScholarDigital Library
- Hitachi Ltd. Hitachi SuperH RISC engine SH7729. Hardware Manual ADE-602--157 Rev. 1.0, Sept. 1999.]]Google Scholar
- D. Kästner. PROPAN: A Retargetable System for Postpass Optimisations and Analyses. In ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, June 2000.]] Google ScholarDigital Library
- C. Kessler and A. Bednarski. A Dynamic Programming Approach to Optimal Integrated Code Generation. In ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, June 2001.]] Google ScholarDigital Library
- C. W. Keßler. Scheduling Expression DAGs for Minimal Register Need. Computer Languages, 24(1): 33--53, Sept. 1998.]]Google ScholarDigital Library
- R. Leupers. Code Optimization Techniques for Embedded Processors. Kluwer, 2000.]] Google ScholarDigital Library
- K. Mehlhorn and S. Näher. LEDA: A Platform for Combinatorial and Geometric Computing. Cambridge University Press, 2000.]] Google ScholarDigital Library
- S. S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann, 1997.]] Google ScholarDigital Library
- Texas Instruments. TMS320C6000 CPU and Instruction Set Reference Guide, October 2000.]]Google Scholar
- S. R. Vegdahl. A Dynamic-Programming Technique for Compacting Loops. In Proc. 25th Annual IEEE/ACM Int. Symp. Microarchitecture, pages 180--188. IEEE Computer Society Press, 1992.]] Google ScholarDigital Library
- T. Wilson, G. Grewal, B. Halley, and D. Banerji. An integrated approach to retargetable code generation. In Proc. International Symposium on High-Level Synthesis, pages 70--75, May 1994.]] Google ScholarDigital Library
Index Terms
- Optimal integrated code generation for clustered VLIW architectures
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