Navid Azizi
Farid N. Najm
ABSTRACT
We introduce a novel family of asymmetric dual-Vt SRAM cell designs that reduce leakage power in caches while maintaining low access latency. Our designs exploit the strong bias towards zero at the bit level exhibited by the memory value stream of ordinary programs. Compared to conventional symmetric high-performance cells, our cells offer significant leakage reduction in the zero state and in some cases also in the one state albeit to a lesser extend. A novel sense-amplifier, in coordination with dummy bitlines, allows for read times to be on par with conventional symmetric cells. With one cell design, leakage is reduced by 7X (in the zero state) with no performance degradation. An alternative cell design reduces leakage by 40X (in the zero state) with a performance degradation of 5%.
- S. Borkar, "Design challenges of technology scaling," IEEE MICRO,vol.19, no.4, pp. 23--29, July--Aug. 1999. Google Scholar
Digital Library
- T. Kam et. al., "EDA challenges facing future microprocessor design," in IEEE Transactions on Computer-Aided Design, vol. 19, no. 12, Dec. 2000. Google ScholarDigital Library
- F. Hamzaoglu et. al., "Dual-Vt SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13um technology generation," in Proc. 2000 Intl. Symp. on Low Power Electronics and Design, July 2000. Google ScholarDigital Library
- John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach (2nd edition), Morgan Kaufman, 1996. Google ScholarDigital Library
- N. Azizi, A. Moshovos, F. N. Najm, B. Falsafi, "Asymmetric-cell caches: exploiting bit value biases to reduce leakage power in deep-submicron, high- performance caches," ECE Computer Group Technical Report TR-01-01-02, Univ. of Toronto.Google Scholar
- E. Seevinck Sr et. al., "Static-noise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, pp. 748--754, Oct. 1987.Google ScholarCross Ref
- V. De, and S. Borkar, "Technology and Design Challenges for Low Power and High Performance Microprocessors," inProc. 1999 Intl. Symp. on Low Power Electronics and Design, 1999. Google ScholarDigital Library
- A. Bhavnagarwala et. al., "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," in IEEE J. of Solid-State Circuits, vol. 36, Apr. 2001.Google Scholar
Index Terms
- Low-leakage asymmetric-cell SRAM
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