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Clock schedule verification with crosstalk

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TAU '02: Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

Pages 78 - 83

https://doi.org/10.1145/589411.589428

Published: 02 December 2002 Publication History

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Abstract

Delay variation due to crosstalk has made timing analysis a hard problem. In sequential circuits with transparent latches, crosstalk makes the clock schedule verification even harder. In this paper, we point out a false negative problem in current clock schedule verification techniques and propose a new approach based on switching windows. In this approach, coupling delay calculations are naturally combined with latch iterations. A novel algorithm is given for clock schedule verification in the presence of crosstalk and primary experiments show promising results.

References

[1]

R. Arunachalam, K. Rajagopal, and L. T. Pilleggi. Taco: Timing analysis with coupling. In Proc. of the Design Automation Conf., pages 266--269, Los Angeles, CA, June 2000.

Digital Library

Google Scholar

[2]

Francois Bourdoncle. Efficient chaotic iteration strategies with widening. In International Conf. on Formal Methods in Programming and Their Applications, LNCS 735, number 735 in LNCS, pages 128--141, 1993.

Digital Library

Google Scholar

[3]

P. Chen, D. A. Kirkpatrick, and K. Keutzer. Switching window computation for static timing analysis in presence of crosstalk noise. In Proc. Intl. Conf. on Computer-Aided Design, San Jose, CA, November 2000.

Digital Library

Google Scholar

[4]

P. Cousot and R. Cousot. Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoints. In ACM Symposium on Principles of Programming Languages, pages 238--252, Los Angeles, CA, January 1977.

Digital Library

Google Scholar

[5]

C. Ebeling and B. Lockyear. On the performance of level-clocked circuits. In Advanced Research in VLSI, pages 242--356, 1995.

Digital Library

Google Scholar

[6]

S. Hassoun. Critical path analysis uing a dynamically bounded delay model. In Proc. of the Design Automation Conf., pages 260--265, Los Angeles, CA, June 2000.

Digital Library

Google Scholar

[7]

Soha Hassoun, Christopher Cromer, and Eduardo Calvillo-Gamez. Verifying clock schedules in the presence of cross talk. In Proc. DATE: Design Automation and Test in Europe, 2002.

Digital Library

Google Scholar

[8]

Kenneth L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993.

Digital Library

Google Scholar

[9]

Karem A. Sakallah, Trevor N. Mudge, and Oyekunle A. Olukotun. checkTc and mintc: Timing verification and optimal clocking of synchronous digital circuits. In Proc. Intl. Conf. on Computer-Aided Design, pages 552--555, November 1990.

Google Scholar

[10]

S. S. Sapatnekar. A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing. IEEE Transactions on Computer Aided Design, 2000.

Digital Library

Google Scholar

[11]

Narendra~V. Shenoy. Timing Issues in Sequential Circuits. PhD thesis, UC Berkeley, 1993.

Google Scholar

[12]

T. G. Szymanski and N. Shenoy. Verifying clock schedules. In Proc. Intl. Conf. on Computer-Aided Design, 1992.

Digital Library

Google Scholar

[13]

H. Zhou, N. Shenoy, and W. Nicholls. Timing analysis with crosstalk as fixpoints on a complete lattice. In Proc. of the Design Automation Conf., pages 714--719, 2001.

Digital Library

Google Scholar

Cited By

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Lin CZhou H(2007)Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With CrosstalkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88827326:7(1222-1232)Online publication date: 1-Jul-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.888273
Lin CZhou H(2005)Trade-off between latch and flop for min-period sequential circuit designs with crosstalkProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129650(329-334)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129650
Chuan Lin Hai Zhou (2005)Trade-off between latch and flop for min-period sequential circuit designs with crosstalkICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.10.1109/ICCAD.2005.1560089(329-334)Online publication date: 2005
https://doi.org/10.1109/ICCAD.2005.1560089

Index Terms

Clock schedule verification with crosstalk
1. Hardware
  1. Hardware validation
    1. Functional verification

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Published In

TAU '02: Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

December 2002

156 pages

ISBN:1581135262

DOI:10.1145/589411

General Chair:
David P. LaPotin
IBM
,
Program Chairs:
Charles J. Alpert
IBM
,
John Lillis
UIC

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 02 December 2002

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TAU02: International Workshop on Timing Issues in the Specifications and Synthesis of Digital Systems

December 2 - 3, 2002

California, Monterey, USA

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TAU '02 Paper Acceptance Rate 19 of 42 submissions, 45%;

Overall Acceptance Rate 19 of 42 submissions, 45%

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Lin CZhou H(2007)Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With CrosstalkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88827326:7(1222-1232)Online publication date: 1-Jul-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.888273
Lin CZhou H(2005)Trade-off between latch and flop for min-period sequential circuit designs with crosstalkProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129650(329-334)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129650
Chuan Lin Hai Zhou (2005)Trade-off between latch and flop for min-period sequential circuit designs with crosstalkICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.10.1109/ICCAD.2005.1560089(329-334)Online publication date: 2005
https://doi.org/10.1109/ICCAD.2005.1560089

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Clock schedule verification under process variations

Verification of Clock Synchronization Algorithms: Experiments on a Combination of Deductive Tools

Low-swing differential conditional capturing flip-flop for LC resonant clock distribution networks

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