ABSTRACT
Growing wire delays will force substantive changes in the designs of large caches. Traditional cache architectures assume that each level in the cache hierarchy has a single, uniform access time. Increases in on-chip communication delays will make the hit time of large on-chip caches a function of a line's physical location within the cache. Consequently, cache access times will become a continuum of latencies rather than a single discrete latency. This non-uniformity can be exploited to provide faster access to cache lines in the portions of the cache that reside closer to the processor. In this paper, we evaluate a series of cache designs that provides fast hits to multi-megabyte cache memories. We first propose physical designs for these Non-Uniform Cache Architectures (NUCAs). We extend these physical designs with logical policies that allow important data to migrate toward the processor within the same level of the cache. We show that, for multi-megabyte level-two caches, an adaptive, dynamic NUCA design achieves 1.5 times the IPC of a Uniform Cache Architecture of any size, outperforms the best static NUCA scheme by 11%, outperforms the best three-level hierarchy--while using less silicon area--by 13%, and comes within 13% of an ideal minimal hit latency solution.
- V. Agarwal, M. S. Hrishikesh, S. W. Keckler, and D. Burger. Clock rate vs. IPC: The end of the road for conventional microprocessors. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 248-259, June 2000. Google ScholarDigital Library
- D. H. Albonesi. Selective cache ways: On-demand cache resource allocation. In Proceedings of the 32nd International Symposium on Microarchitecture, pages 248-259, December 1999. Google ScholarDigital Library
- D. Bailey, J. Barton, T. Lasinski, and H. Simon. The NAS parallel benchmarks. Technical Report RNR-91-002 Revision 2, NASA Ames Research Laboratory, Mountain View, CA, August 1991.Google Scholar
- F. Bodin and A. Seznec. Skewed associativity enhances performance predictability. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 265-274, June 1995. Google ScholarDigital Library
- F. Dahlgren and P. Stenström. On reconfigurable on-chip data caches. In Proceedings of the 24th International Symposium on Microarchitecture, pages 189-198, November 1991. Google ScholarDigital Library
- R. Desikan, D. Burger, S. W. Keckler, and T. M. Austin. Sim-alpha: A validated execution-driven alpha 21264 simulator. Technical Report TR-01-23, Department of Computer Sciences, University of Texas at Austin, 2001.Google Scholar
- A. González, C. Aliagas, and M. Valero. A data cache with multiple caching strategies tuned to different types of locality. In Proceedings of the 1995 International Conference on Supercomputing, pages 338-347, July 1995. Google ScholarDigital Library
- L. Gwennap. Alpha 21364 to ease memory bottleneck. Microprocessor Report, 12(14), October 1998.Google Scholar
- E. G. Hallnor and S. K. Reinhardt. A fully associative software-managed cache design. In Proceedings of the 27th International Symposium on Computer Architecture, pages 107-116, June 2000. Google ScholarDigital Library
- J. M. Hill and J. Lachman. A 900MHz 2.25 MB cache with on-chip CPU now in Cu SOI. In Proceedings of the IEEE International Solid-State Circuits Conference, pages 171-177, February 2001.Google Scholar
- M. Horowitz, R. Ho, and K. Mai. The future of wires. In Seminconductor Research Corporation Workshop on Interconnects for Systems on a Chip, May 1999.Google Scholar
- M. S. Hrishikesh, Norman P. Jouppi, Keith I. Farkas, Doug Burger, Stephen W. Keckler, and Premkishore Shivakumar. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays. In Proceedings of the 29th Annual International Symposium on Computer Architecture, pages 14-24, May 2002. Google ScholarDigital Library
- J. Huh, D. Burger, and S. W. Keckler. Exploring the design space of future CMPs. In Proceedings of the 10th International Conference on Parallel Architectures and Compilation Techniques, pages 199-210, September 2001. Google ScholarDigital Library
- J. Rubinstein, P. Penfield, and M. A. Horowitz. Signal delay in RC tree networks. IEEE Transactions on Computer-Aided Design, CAD-2(3):202-211, 1983.Google Scholar
- T. L. Johnson and W. W. Hwu. Run-time adaptive cache hierarchy management via reference analysis. In Proceedings of the 24th Annual International Symposium on Computer Architecture, pages 315-326, June 1997. Google ScholarDigital Library
- N. Jouppi and S. Wilton. An enhanced access and cycle time model for on-chip caches. Technical Report TR-93-5, Compaq WRL, July 1994.Google Scholar
- R. E. Kessler. Analysis of Multi-Megabyte Secondary CPU Cache Memories. PhD thesis, University of Wisconsin-Madison, December 1989. Google ScholarDigital Library
- R. E. Kessler. The alpha 21264 microprocessor. IEEE Micro, 19(2):24-36, March/April 1999. Google ScholarDigital Library
- R. E. Kessler, M. D. Hill, and D. A. Wood. A comparison of trace-sampling techniques for multi-megabyte caches. IEEE Transactions on Computers, 43(6):664-675, June 1994. Google ScholarDigital Library
- R. E. Kessler, R. Jooss, A. Lebeck, and M. D. Hill. Inexpensive implementations of set-associativity. In Proceedings of the 16th Annual International Symposium on Computer Architecture, pages 131-139, May 1989. Google ScholarDigital Library
- K.-F. Lee, H.-W. Hon, and R. Reddy. An overview of the SPHINX speech recognition system. IEEE Transactions on Acoustics, Speech and Signal Processing, 38(1):35-44, 1990.Google ScholarCross Ref
- D. Matzke. Will physical scalability sabotage performance gains? IEEE Computer, 30(9):37-39, September 1997. Google ScholarDigital Library
- H. Pilo, A. Allen, J. Covino, P. Hansen, S. Lamphier, C. Murphy, T. Traver, and P. Yee. An 833MHz 1.5w 18Mb CMOS SRAM with 1.67Gb/s/pin. In Proceedings of the 2000 IEEE International Solid-State Circuits Conference, pages 266-267, February 2000.Google Scholar
- M. D. Powell, A. Agarwal, T. N. Vijaykumar, B. Falsafi, and K. Roy. Reducing set-associative cache energy via way-prediction and selective direct-mapping. In Proceedings of the 34th International Symposium on Microarchitecture, pages 54-65, December 2001. Google ScholarDigital Library
- S. A. Przybylski. Performance-Directed Memory Hierarchy Design. PhD thesis, Stanford University, September 1988. Technical report CSL-TR-88-366. Google ScholarDigital Library
- The national technology roadmap for semiconductors. Semiconductor Industry Association, 1999.Google Scholar
- P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power and area model. Technical report, Compaq Computer Corporation, August 2001.Google Scholar
- K. So and R. N. Rechtshaffen. Cache operations by MRU change. IEEE Transactions on Computers, 37(6):700-109, July 1988. Google ScholarDigital Library
- G. S. Sohi and M. Franklin. High-performance data memory systems for superscalar processors. In Proceedings of the Fourth Symposium on Architectural Support for Programming Languages and Operating Systems, pages 53-62, April 1991. Google ScholarDigital Library
- Standard Performance Evaluation Corporation. SPEC Newsletter, Fairfax, VA, September 2000.Google Scholar
- G. Tyson, M. Farrens, J. Matthews, and A. Pleszkun. A modified approach to data cache management. In Proceedings of the 28th International Symposium on Microarchitecture, pages 93-103, December 1995. Google ScholarDigital Library
- K. M. Wilson and K. Olukotun. Designing high bandwidth on-chip caches. In Proceedings of the 24th Annual International Symposium on Computer Architecture, pages 121-132, June 1997. Google ScholarDigital Library
- S. Wilton and N. Jouppi. Cacti: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, 31(5):677-688, May 1996.Google ScholarCross Ref
- An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
Recommendations
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
Special Issue: Proceedings of the 10th annual conference on Architectural Support for Programming Languages and Operating SystemsGrowing wire delays will force substantive changes in the designs of large caches. Traditional cache architectures assume that each level in the cache hierarchy has a single, uniform access time. Increases in on-chip communication delays will make the ...
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
Growing wire delays will force substantive changes in the designs of large caches. Traditional cache architectures assume that each level in the cache hierarchy has a single, uniform access time. Increases in on-chip communication delays will make the ...
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
Growing wire delays will force substantive changes in the designs of large caches. Traditional cache architectures assume that each level in the cache hierarchy has a single, uniform access time. Increases in on-chip communication delays will make the ...
Comments