François-Xavier Standaert
ABSTRACT
Reprogrammable devices such as Field Programmable Gate Arrays (FPGA's) are highly attractive options for hardware implementations of encryption algorithms and this report investigates a methodology to efficiently implement block ciphers in CLB-based FPGA's. Our methodology is applied to the new Advanced Encryption Standard RIJNDAEL and the resulting designs offer better performances than previously published in literature. We propose designs that unroll the 10 AES rounds and pipeline them in order to optimize the frequency and throughput results. In addition, we implemented solutions that allow to change the plaintext and the key on a cycle-by-cycle basis with no dead cycles. Another strong focus is placed on low area circuits and we propose sequential designs with very low area requirements. Finally we demonstrate that RAM-based implementations implies different constraints but our methodology still holds.
- Xilinx: Virtex 2.5V Field Programmable Gate Arrays Data Sheet, http://www.xilinx.com.]]Google Scholar
- J.Daemen and V.Rijmen, The Block Cipher RIJNDAEL, NIST's AES home page, http://www.nist.gov/aes.]]Google Scholar
- A.J.Elbirt et Al, An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists, The Third Advanced Encryption Standard (AES3) Candidate Conference, April 13--14 2000, New York, USA.]]Google Scholar
- K.Gaj and P.Chodowiec, Comparison of the Hardware Performance of the AES Candidates using Reconfigurable Hardware, The Third Advanced Encryption Standard (AES3) Candidate Conference, April 13--14 2000, New York, USA.]]Google Scholar
- P.Chodowiec et al, Experimental Testing of the Gigabit IPSec-Compliant Implementations of RIJNDAEL and Triple-DES Using SLAAC-1V FPGA Accelerator Board, in the proceedings of ISC 2001: Information Security Workshop, LNCS 2200, pp.220--234, Springer-Verlag.]] Google ScholarDigital Library
- A.Dandalis et al, A Comparative Study of Performance of AES Candidates Using FPGA's, The Third Advanced Encryption Standard (AES3) Candidate Conference, April 13--14 2000, New York, USA.]] Google ScholarDigital Library
- T.Ichikawa et al, Hardware Evaluation of the AES Finalists, The Third Advanced Encryption Standard (AES3) Candidate Conference, April 13--14 2000, New York, USA.]]Google Scholar
- O.Kwon et al, Implementation of AES and Triple-DES Cryptography using a PCI-based FPGA Board, in the proceedings of ITC-CSCC 2002: The International Technical Conference On Circuits/Systems, Computers and Communications.]]Google Scholar
- M.McLoone and J.V.McCanny, High Performance Single Ship FPGA RIJNDAEL Algorithm Implementations, in the proceedings of CHES 2001: The Third International CHES Workshop, Lecture Notes In Computer Science, LNCS2162, pp 65--76, Springer-Verlag.]] Google ScholarDigital Library
- M.McLoone and J.V.McCanny, Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm, in the proceedings of FPL 2002: The Field Programmable Logic Conference, Lecture Notes in Computer Science, LNCS 2147, p.152ff.]] Google ScholarDigital Library
- Helion Technology, High Performance AES (Rijndael) Cores for XILINX FPGA, http://www.heliontech.com.]]Google Scholar
- V.Fischer and M.Drutarovsky, Two Methods of RIJNDAEL Implementation in Reconfigurable Hardware, in the proceedings of CHES 2001: The Third International CHES Workshop, Lecture Notes In Computer Science, LNCS2162, pp 65--76, Springer-Verlag.]] Google ScholarDigital Library
- A.Rudra et al, Efficient RIJNDAEL Encryption Implementation with Composite Field Arithmetic, in the proceedings of CHES 2001: The Third International CHES Workshop, Lecture Notes In Computer Science, LNCS2162, pp 65--76, Springer-Verlag.]] Google ScholarDigital Library
- A.Satoh et al, A Compact RIJNDAEL Hardware Architecture with S-Box Optimization, Advances in Cryptology - ASIACRYPT 2001, LNCS 2248, pp239--254, Springer-Verlag.]] Google ScholarDigital Library
- CAST, AES Encryption Cores, http://www.cast-inc.com.]]Google Scholar
Index Terms
- A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL
Recommendations
64-bit Block ciphers: hardware implementations and comparison analysis
A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide ...
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
Wireless networks are very widespread nowadays, so secure and fast cryptographic algorithms are needed. The most widely used security technology in wireless computer networks is WPA2, which employs the AES algorithm, a powerful and robust cryptographic ...
Study of the AES Realization Method on the Reconfigurable Hardware
CSA '13: Proceedings of the 2013 International Conference on Computer Sciences and ApplicationsIn order to improve the realization efficiency of AES encryption algorithm based on FPGA and reduce hardware resource utilization. We give a reconfigurable implementation of AES encryption and decryption circuit which supports three different key ...
Comments