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ABSTRACT
Feedback from users of the first generation ISP system plus the development and availability of new VLSI based technologies drove the design of the iPSC/2 node. The new node design was broadly governed by the following goals:
Provide true 32-bit node architecture and performance.
Match the communication performance to the computational performance.
Increase on board memory capacity by using new RAM technology.
Employ a modular functional elements to easily incorporate future technology.
Allow plug compatibility with existing iPSC systems, including interface to co-processors.
Ensure software compatibility for existing iPSC applications.
This paper describes how the iPSC/2 node achieved these goals by leveraging Intel's VLSI expertise and products, surface mount, CMOS and gate array technologies, and small daughter boards to implement modular subsystems.
- 1.Nugent, Steve, TheiPSCI2 Direct-Connect Technology, Proceedings, 3rd Conference on Hypercube Concurrent Computers and Applications, 1988. Google Scholar
Digital Library
Index Terms
- The iPSC/2 node architecture
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