C.-Y. Lo
ABSTRACT
This paper describes a new algorithm that automatically generates tub regions for VLSI symbolic layouts with quality comparable to that of human designers. The algorithm supports an explicit modeling of enclosure rules in the layout compaction task with the benefit of robustness and reduced output database size. In addition, the algorithm runs at O(n2) time and O(n) space with the expected run time of O(nlogn).
- LoLa80.A.D. Lopez and H-F. S. Law, " A dense gate matrix layout style for MOS LSI," IEEE J. of Solid-State Circuits, Vol SC-15, No. 4, August 1980, pp. 736- 740.Google Scholar
Cross Ref
- West81.N,H.E, Weste, "MULGA - an interactive symbolic layout system for the design of integrated circuits," Bell System Technical Journal 60(6) pp, 823-857 (July-Aug. 1981).Google ScholarCross Ref
- Fis85.J.P. Fishburn and A.E. Dunlop, 'q'}I,OS: a posynomial programming approach to tJ:ansistor sizing," Digest 1nil. Conf. on Compute.r-Aided Design, pp. 326-328, November 1985.Google Scholar
- Var85.Ravl Varadarajan, "Algorithms for circuit layout compaction of building blocks," Master of Science thesis, Texas Tech University, December, 1985.Google Scholar
- PrSh85.F.P. Pleparata and M.I. Shamos, "Computational geometry: an introduction," Springer-Verlag, 1985. Google ScholarDigital Library
- RaCS86.Raghunath Raghavan, James Cohoon and Sartaj Sahni," Single Bend Wiring," Journal of Algorithms 7, pp 232-257, 1986. Google ScholarDigital Library
- Boy87.D.G. Boyer, "Symbolic layout compaction benchmarks results," Digest Intl. Conf. on Computer Design, pp. 209-217, October, 1987.Google Scholar
- Cro87.W.H. Crocker, R. Varadarajan and C.-Y. Lo, "MACS: a module assembly and compaction system," Digest Intl. Conf. on Computer Design, pp. 205-208, October, 1987.Google Scholar
- DoSo87.D. Dobkin and D.L. Souvaine, "Computational geometry - a user's guide," in "Advances in Robotics" Vol, 1, edited by LT. Sehwarts and C-K. Yap, Lawrence Erlbaum Associates, Inc, 1987.Google Scholar
- LiNe87.B. Lin and A. R. Newton, "KAI~{LUA: a hierarchical circuit disassembler," Proceedings 24-th Design Automation Conference, pp. 311-317, June 1984. Google ScholarDigital Library
- ShHi88.D.D. Shugard and D.D. Hill, "rub insertion for hierarclfical CMOS designs," AT&T Bell Laboratories Technical Memorandum TM 11253- 880203-03, Feb. 1988.Google Scholar
- Lee88.J.-F. Lee, "A new framework of design rules for compaction of VLSI layouts," IEEE Transactions on Computer-Aided Design, pp. 1195-1204, Volume 7, Ntmtber 11, November 1988.Google Scholar
- CoRi88.J.P. Cohoon and D.S. Richards, "Optimal twoterminal 0t-~ wire routing," IM'EGRATION, the VLSI journal 6, pp. 35-57, 1988. Google ScholarDigital Library
Index Terms
- Automatic tub region generation for symbolic layout compaction
Recommendations
Symbolic layout compaction review
DAC '88: Proceedings of the 25th ACM/IEEE Design Automation ConferenceSymbolic layout and compaction is reaching a mature status. This is demonstrated, in part, by the recent or imminent introductions of a number of commercial symbolic layout and compaction systems. The two most frequently used symbolic layout compaction ...
Comments