Yu Chen
Andrew B. Kahng
ABSTRACT
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertions. We then give the first formulations of the Performance Impact Limited Fill (PIL-Fill) problem with the objective of either minimizing total delay impact (MDFC) or maximizing the minimum slack of all nets (MSFC), subject to inserting a given prescribed amount of fill. For the MDFC PIL-Fill problem, we describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. For the MSFC PIL-Fill problem, we describe an iterated greedy method that integrates call to an industry static timing analysis tool. We test our methods on layout testcases obtained from industry. Compared with the normal fill method [3], our ILP-II method for MDFC PIL-Fill problem achieves between 25-% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact while maintaining identical quality of the layout density control; and our iterated greedy method for MSFC PIL-Fill problem also shows significant advantage with respect to the minimum slack of nets on post-fill layout.
- N. D. Arora, K. V. Raol, R. Schumann, and L. M. Richardson, "Modeling and Extraction of Interconnect Capacitances for Multi-layer VLSI Circuits," IEEE Trans. on Computer-Aided Design 15(1) (1996), pp. 58--67. Google Scholar
Digital Library
- E. Barke, "Line-to-Ground Capacitance Calculation for VLSI: A Comparison", IEEE Trans. on Computer-Aided Design 7(2) (1988), pp. 295--298.Google ScholarDigital Library
- Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Dummy Fill Synthesis for Uniform Layout Density", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21(10) (2002), pp. 1132--1147. Google ScholarDigital Library
- Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Smoothness and Uniformity of Filled Layout for VDSM Manufacturability," Proc. ACM/IEEE International Symposium on Physical Design, April 2002, pp. 137--142. Google ScholarDigital Library
- J. Chern, J. Huang, L. Aldredge, P. Li and P. Yang, "Multilevel Metal Capacitance Models for Interconnect Capacitances", IEEE Electron Device Lett EDL-14 (1992), pp. 32--43.Google Scholar
- J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", Proc. ACM/IEEE Design Automation Conf., 1997, pp. 627--632. Google ScholarDigital Library
- W. C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers", Journal of Applied Physics (1948), pp. 55--63.Google ScholarCross Ref
- W. Grobman, M. Thompson, R. Wang, C. Yuan, R. Tian, and E. Demircan, "Reticle Enhancement Technology: Implications and Challenges for Physical Design ", Proc. ACM/IEEE Design Automation Conf., 2001, pp. 73--78. Google ScholarDigital Library
- A. B. Kahng, S. Muddu and E. Sarto, "On Switch Factor Based Analysis of Coupled RC Interconnects", Proc. ACM/IEEE Design Automation Conf., 2000, pp. 79--84. Google ScholarDigital Library
- Praesagus, Inc., http://www.praesagus.com/Google Scholar
- B. E. Stine, D. S. Boning et al., "The Physical and Electrical Effects of Metal Fill Patterning Practices for Oxide Chemical Mechanical Polishing Processes", IEEE Trans. on Electron Devices 45(3) (1998), pp. 665--679.Google ScholarCross Ref
- A. Toulouse, D. Bernard, C. Landrault and P. Nouet "Efficient 3D Modeling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts", Proc. Design Automation and Test Europe, 1999, pp. 576--580. Google ScholarDigital Library
- UbiTech. Inc., http://www.ubitechnology.com/Google Scholar
- XYALIS, http://www.xyalis.com/Google Scholar
Index Terms
- Performance-impact limited area fill synthesis
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