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Static noise analysis with noise windows

Published:02 June 2003Publication History

ABSTRACT

As processing technology scales down to the nanometer regime, capacitive crosstalk is having an increasingly adverse effect on circuit functionality, leading to increasing number of chip failures. In this paper, we propose mapping the static crosstalk functional noise problem into the well understood static timing problem. The key differences between static noise and static timing analyses, namely the injection of noise, accurate noise window propagation and register sensitive window computation are the contributions of this work. We demonstrate the effectiveness of this approach in two industrial designs by achieving 5X reduction in functional noise failures over noise propagation without considering timing of the composite noise pulse envelope, and 30X reduction in functional noise failures over net based noise failure metrics.

References

  1. K. L. Shepard and V. Narayanan, "Noise in Deep Submicron Digital Design", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 524--531, November 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. P.Chen, K.Keutzer, "Towards True Crosstalk Noise Analysis", International Conference on Computer-Aided Design, pp.132--137, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Xiao, T., Marek-Sadowska, M. "Worst delay estimation in crosstalk aware static timing analysis", International Conference on Computer Design, 2000, pp. 115--120. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Scheffer, L. "What is the appropriate model for crosstalk control?" 13th Symposium on Integrated Circuits and Systems Design, 2000, pp. 315--320. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. C. J. Alpert, A. Devgan, S. T. Quay, "Buffer Insertion for Noise and Delay Optimization", IEEE Transactions on Computer-Aided Design, pp. 1633--1645, November 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Hui Chen, L.; Marek-Sadowska, M., "Aggressor alignment for worst-case crosstalk noise", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume: 20 Issue: 5 , May 2001, pp. 612--621. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Shepard, K.L.; Chou, K. "Cell characterization for noise stability", Custom Integrated Circuits Conference, 2000, pp. 91--94.Google ScholarGoogle Scholar
  8. CeltIC User Guide, Cadence Design Systems, 2002.Google ScholarGoogle Scholar
  9. PacifIC User Guide, Cadence Design Systems, 2002.Google ScholarGoogle Scholar
  10. Levy, R.; Blaauw, D.; Braca, G.; Dasgupta, A.; Grinshpon, A.; Chanhee Oh; Orshav, B.; Sirichotiyakul, S.; Zolotov, V. "ClariNet: a noise analysis tool for deep submicron design", Design Automation Conference, 2000, pp. 233--238 Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Zolotov, V.; Blaauw, D.; Sirichotiyakul, S.; Becer, M.; Oh, C; Panda, R; Grinshpon, A.; Levy, R.; "Noise Propagation and Failure Criteria for VLSI Designs", International Conference on Computer Aided Design, pp. 587--594, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Bryant, R. E., "Extraction of gate level models from transistor circuits by four-valued symbolic analysis", International Conference on Computer Aided Design, pp. 350--353, 1991.Google ScholarGoogle ScholarCross RefCross Ref
  13. Kuehlmann, A., Srinivasan, A., LaPotin, D. P., "Verity - A formal verification program for custom CMOS circuits", IBM J. Res. Development, Vol. 39, No. 1/2, pp. 149--165, Jan/Mar 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Bryant, R. E., "Graph-based algorithm for boolean function manipulation", IEEE Trans. Computers, Vol. 35, No. 8, pp. 677--691, Aug. 1986. Google ScholarGoogle ScholarDigital LibraryDigital Library

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    • Published in

      cover image ACM Conferences
      DAC '03: Proceedings of the 40th annual Design Automation Conference
      June 2003
      1014 pages
      ISBN:1581136889
      DOI:10.1145/775832

      Copyright © 2003 ACM

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      Publication History

      • Published: 2 June 2003

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