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ASPLOS I: Proceedings of the first international symposium on Architectural support for programming languages and operating systems
ACM1982 Proceeding
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
Conference:
Palo Alto California USA March 1 - 3, 1982
ISBN:
978-0-89791-066-8
Published:
01 March 1982
Sponsors:
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Hardware/software cooperation in the iAPX-432

The Intel iAPX-432 is an object-based microcomputer system with a unified approach to the design and use of its architecture, operating system, and primary programming language. The concrete architecture of the 432 incorporates hardware support for data ...

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Free
Hardware/software tradeoffs for increased performance

Most new computer architectures are concerned with maximizing performance by providing suitable instruction sets for compiled code and providing support for systems functions. We argue that the most effective design methodology must make simultaneous ...

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Coding guidelines for pipelined processors

This paper is a tutorial for assembly language programmers of pipelined processors. It describes the general characteristics of pipelined processors and presents a collection of coding guidelines for them. These guidelines are particularly significant ...

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An overview of the mesa processor architecture

This paper provides an overview of the architecture of the Mesa processor, an architecture which was designed to support the Mesa programming system [4]. Mesa is a high level systems programming language and associated tools designed to support the ...

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The operating system and language support features of the BELLMACTM-32 microprocessor.

The BELLMAC-32 microprocessor is a 32-bit microprocessor, implemented with CMOS technology, designed to support operating system functions and high level languages efficiently. The architecture was designed with the following objectives in mind:

• High ...

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The 801 minicomputer

This paper provides an overview of an experimental system developed at the IBM T. J. Watson Research Center. It consists of a running hardware prototype, a control program and an optimizing compiler. The basic concepts underlying the system are ...

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Register allocation for free: The C machine stack cache

The Bell Labs C Machine project is investigating computer architectures to support the C programming language.1 One of the goals is to match an efficient architecture to the language and the compiler technology available. Measurements of different C ...

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An architectural alternative to optimizing compilers

Programming languages are designed to make programming productive. Computer architectures are designed to make program execution efficient. Although architectures should be designed with programming languages in mind, it may be as inappropriate to make ...

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Fast procedure calls

A mechanism for control transfers should handle a variety of applications (e.g., procedure calls and returns, coroutine transfers, exceptions, process switches) in a uniform way. It should also allow an implementation in which the common cases of ...

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Systematic protection mechanism design

This work describes an attempt to systematically design a hardware resource protection mechanism when given the requirements of a particular language as a target. The design process is formalized as a structured walk through the multidimensional ...

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On a general property of memory mapping tables

The paper shows that memory mapping tables can be used to implement the display registers used in providing architectural support for block-structured languages such as Algol 60. This allows full lexical level addressing to be implemented on so-called ...

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An experiment to improve operand addressing

MCODE is a high-level language, stack machine designed to support strongly-typed, Pascal-based languages with a variety of data types in a modular programming environment. The instruction set, constructed for efficiency and extensibility, is based on an ...

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Compiler chip: A hardware implementation of compiler

In this paper we discuss about another approch: Compiler Chip, which is a VLSI implementation of a compiler. Constructing a compiler by a few VLSI chip, the computer manufacturer can deliver compilers by sets of VLSI chips, and these chips are installed ...

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Architectural support for the efficient generation of code for horizontal architectures

Horizontal architectures, such as the CDC Advanced Flexible Processor [I] and the FPS APi20-B [2}, consist of a number of resources that can operate in parallel, each of which is controlled by a field in the wide instruction word. Such architectures ...

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Guidelines for creating a debuggable processor

Hardware without software is of little use. Systems that ease the task of debugging software reduce cost and speed development. This paper presents guidelines for designing processors that ease debugging for real-time computer systems. Special hardware ...

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Hardware support for memory protection: Capability implementations

This paper is intended to stimulate discussion on the present state of hardware supported capability systems. Interest in such systems grew up in the mid-1960's and since that time information has been published on several different versions. In the ...

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Supporting ada memory management in the iAPX-432

In this paper, we describe how the memory management mechanisms of the Intel iAPX-432 are used to implement the visibility rules of Ada. At any point in the execution of an Ada® program on the 432, the program has a protected address space that ...

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Direct execution of lisp on a list_directed architecture

We have defined a direct-execution model dedicated to non-numerical processing which is based upon an internal representation of source programs derived from LISP. This model provides good support for both sophisticated editing (syntactical parsing, ...

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Some requirements for architectural support of software debugging

Architectural support of high-level, symbolic debugging is described at three levels of abstraction: the user's view of desired debugging functionality, the debugger implementor's view of architectural requirements that support the functionality, and ...

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The effect of the PDP-11 architecture on code generation for chill

This paper outlines the implementation of the CCITT*) high level programming language CHILL on PDP-11 computers in the CHILL compiler constructed at the Dr. Neher Laboratories. The characteristics and structure of the compiler are briefly described. The ...

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Empirical analysis of the mesa instruction set

This paper describes recent work to refine the instruction set of the Mesa processor. Mesa [8] is a high level systems implementation language developed at Xerox PARC during the middle 1970's. Typical systems written in Mesa are large collections of ...

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An analysis of a mesa instruction set using dynamic instruction frequencies

The Mesa architecture is implemented on a variety of processors, and dynamic instruction frequency data for two programs is used to analyze the architecture in an implementation independent fashion.

The Mesa compiler allocates variables in an order ...

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A case study of VAX-11 instruction set usage for compiler execution

Analysis of an instruction set as large and varied as the one specified for the VAX-11 architecture is important for aiding processor design evaluation. This paper looks at dynamic VAX-11 instruction set usage by one class of programs, and discusses the ...

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Firmware structure and architectural support for monitors, vertical migration and user microprogramming

This paper describes firmware and hardware support necessary for constructing easy-to-understand and high performance operating systems including language translators and interpreters. Basic principles are one-to-one correspondence between logical ...

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Heart: An operating system nucleus machine implemented by firmware

This paper discusses the role of microprogramming in operating system design and shows several things: (1) advantages of the efficiency which may be gained from microcoded operating system primitives, (2) selecting the most appropriste primitives for ...

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A multi-microprocessor architecture with hardware support for communication and scheduling

We describe a multiprocessor system that attempts to enhance the system performance by incorporating into its architecture a number of key operating system concepts. In particular:

— the scheduling and synchronization of concurrent activities are built ...

Contributors
  • Intel Corporation

Index Terms

  1. Proceedings of the first international symposium on Architectural support for programming languages and operating systems

      Recommendations

      Acceptance Rates

      Overall Acceptance Rate 535 of 2,713 submissions, 20%
      YearSubmittedAcceptedRate
      ASPLOS '193517421%
      ASPLOS '183195618%
      ASPLOS '173205317%
      ASPLOS '162325323%
      ASPLOS '152874817%
      ASPLOS '142174923%
      ASPLOS XV1813218%
      ASPLOS XIII1273124%
      ASPLOS XII1583824%
      ASPLOS X1752414%
      ASPLOS IX1142421%
      ASPLOS VIII1232823%
      ASPLOS VII1092523%
      Overall2,71353520%