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ISCA '73: Proceedings of the 1st annual symposium on Computer architecture
ACM1973 Proceeding
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
Conference:
December 9 - 11, 1973
ISBN:
978-1-4503-7428-6
Published:
09 December 1973
Sponsors:
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Markov chain models for analyzing memory interference in multiprocessor computer systems

This paper discusses various analytical techniques for studying the extent of memory interference in a multiprocessor system with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory ...

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Interconnecting a distributed processor system for avionics

This paper describes the interconnection scheme devised for an advanced Air Force system concept called Distribution Processor/Memory (DP/M) in which topologically irregular networks of small computers are used to perform avionics processing. The ...

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Banyan networks for partitioning multiprocessor systems

This paper describes a class of partitioning networks, called banyans, whose cost function grows more slowly than that of the crossbar and whose fan-out requirements are independent of network size. Such networks can economically partition the resources ...

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Structure of digital system description languages

Several languages have been developed for or applied to the problem of describing digital hardware systems. This paper points out some of the problems encountered in hardware descriptions, particularly where they are distinct from concepts appearing in ...

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VDL—a Definition system for all levels

The VDL system for the description of programming languages which was originally used for the definition of PL/I is extended to the description of processors. This paper shows the relationship between the language of definition and the abstract machine ...

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A methodology for parallel processing design tradeoffs

A methodology is developed for determining how much parallelism is optimal if a given job stream is to be executed without multiprogramming. Qualitative design tradeoffs are inferred from the cost-performance effect of parallelism on different hardware ...

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DAP—a distributed array processor

An array of very simple processing elements is described each with a local semiconductor store. The array may also be used as main storage.

Bit-organisation gives great flexibility, including the minimisation of word length. Use of MSI and LSI is helped ...

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Maximal rate pipelined solutions to recurrence problems

An m thorder recurrence problem is defined as the computation of X1, . . . XN, where Xi=f (ai, Xi-1, . . Xi-m) and ai is a set of parameters. On a pipelined computer, where the total stage delay in computing f is df time units, the solution output rate ...

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Comments on capabilities, limitations and “correctness” of Petri nets

In this paper we examine the capabilities and limitations of Petri nets and investigate techniques for proving their correctness. We define different classes of nets where each is basically a Petri net with slight modifications and study the ...

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Flowware—a flow charting procedure to describe digital networks

FLOWWARE is an interactive, graphical language to aid in the understanding and design of digital networks. The language is based upon the concept of flow charting. The user specifies the register layout of the network and the sequential operation in the ...

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Automated exploration of the design space for register transfer (RT) systems

A Design Automation System for the RT level of design is described. The System explores the design space by finding alternative implementations for a user given behavioral specification. The alternative solutions are obtained by transformations on a ...

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Implementation aspects of the symbol hardware compiler

One of the most outstanding features of the SYMBOL computer is its high level hardware compiler. This paper presents some aspects of the hardware implementation including the network characteristics of the communication scheme between compiler, system ...

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The architecture of CASSM: A cellular system for non-numeric processing

This paper presents the architecture of a context-addressed cellular system for non-numeric information processing, using an inexpensive, large-capacity circulating memory device. The system allows data to be represented in a structure very close to the ...

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Deriving design guidelines for diagnosable computer systems

Diagnosable computer systems are designed to detect and isolate the faults that occur during system operation. A number of techniques are available to the system designer of diagnosable systems. This paper examines a number of these techniques and ...

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Design of fault-tolerant associative processors

Recent advances in computer technology have made the design of large and very flexible associative processors possible. Such systems are extremely complex and must be adequately protected against failures if they are to be used in critical application ...

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A fault tolerant multiprocessor architecture for real-time control applications

This paper presents a fault tolerant multiprocessor architecture suitable for real time control applications requiring an extremely high degree of reliability. The architecture satisfies the following requirements:

l) Ability to deal with software as ...

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A varistructured fail-soft cellular computer

The architecture of a von-Neumann class computer is considered, in which the user programmer can request, at the beginning of his task, one of many word widths, and one of many memory heights. Several users are able to space share the computer. We call ...

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A hardware laboratory for computer architecture research

Because of dramatic reductions in cost of mini-computers, peripherals and logic modules, it is becoming evident that many problems confronting the computer system designer will be solved in the future by hybrid designs involving not only software but ...

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Simulation exercises for computer architecture education

In a case studies approach to computer architecture education, there is a need for small-scale simulation exercises to illustrate significant concepts and to provide hands-on student experience with architectural tradeoffs. Two such exercises are ...

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Computer architecture courses in electrical engineering departments

This paper traces the history of computer architecture courses in electrical engineering departments. Previously unpublished data from the Fall 1972 COSINE survey are given to show current computer architecture course offerings and texts. Computer ...

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Increasing hardware complexity—a challenge to computer architecture education

The paper starts with a survey over history and present-day situation of educational concepts and design methods in computer architecture. Complexity problems, bad design habits, cooperation problems between specialists, as well as their changing range ...

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Review of the workshop on computer architecture education

This paper reviews the presentations and discussions of the participants in the Workshop on Education and Computer Architecture held in Atlanta, Georgia on 30 August 1973.

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Micromodules: Microprogrammable building blocks for hardware development

The purpose of the Micromodules project is to greatly reduce the amount of effort expended on logic design, fabrication and debug for small quantity developments. Secondly, with this modular approach, a quick reaction capability is sought that would ...

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Computer Modules: An architecture for large digital modules

This paper describes the architecture of Computer Modules, or CMs. They are large digital modules of about minicomputer complexity that are specifically designed to take advantage of the rapidly advancing semiconductor technology. These modules are ...

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A microprogrammed architecture for front end processing

The increasing diversity of hardware devices and software procedures developed for remote processing has yielded a multiplicity of new facilities and telecommunication network structures. The corresponding architectures for front-end systems range from ...

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Design of a fully variable-length structured minicomputer

Binary-based and fixed-length structure computers are often inconvenient and wasteful of resources. In this paper we present a design for a fully variable-length structured minicomputer. Since all parameters (instructions and data) are unrestricted in ...

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Happe Honeywell Associative Parallel Processing Ensemble

Many problems, inherent in air traffic control, weather analysis and prediction, nuclear reaction, missile tracking, and hydrodynamics have common processing characteristics that can most efficiently be solved using parallel “non-conventional” ...

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A computer architecture and its programming language

Computer architectures and programming languages are traditionally developed independently. Through suitable computer architecture, for instance, one can attempt to speed up the processing of a stream of data and instructions, leaving to the software ...

Contributors
  • University of Florida
  • Southern Methodist University

Index Terms

  1. Proceedings of the 1st annual symposium on Computer architecture

    Recommendations

    Acceptance Rates

    Overall Acceptance Rate 543 of 3,203 submissions, 17%
    YearSubmittedAcceptedRate
    ISCA '224006717%
    ISCA '193656217%
    ISCA '173225417%
    ISCA '132885619%
    ISCA '122624718%
    ISCA '082593714%
    ISCA '062343113%
    ISCA '051944523%
    ISCA '042173114%
    ISCA '031843620%
    ISCA '021802715%
    ISCA '011632415%
    ISCA '991352619%
    Overall3,20354317%