Lionel C. Bening
ABSTRACT
This paper presents a design verification logic simulation system which uses a ccurate timing information and propagation delay ambiguity in its circuit models.
The case in favor of such a system is put forth. Methods for simulating propagation delay ambiguity and utilizing accurate circuit timing data are introduced. The time-sequenced simulation programming technique used in this system is described. Host computer memory and time requirement data from simulation test runs are reported.
- 1.G. G. Langdon, "Analysis of Asynchronous Circuits Under Different Delay Assumptions," IEEE Trans. Computers, Vol. C17, pp. 1131-1143, December 1968.Google Scholar
Digital Library
- 2.E. G. Ulrich, "Time-Sequenced Logical Simulation Based on Circuit Delay and Selective Tracing of Active Network Paths", Proc. ACM 20th National Conference 1965, pp. 437-448 Google ScholarDigital Library
- 3.Fairsim Users Manual, Fairchild Semiconductor Publ. 61-BR-0034-78/4M. Mountain View, California: Fairchild Semiconductor, 1968.Google Scholar
Index Terms
- Accurate simulation of high speed computer logic
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