Mario R. Casu
Luca Macchiarulo
ABSTRACT
Large Systems-on-Chip (SoC) in advanced technologies run at such high frequencies that the time-of-flight of signals connecting two distant pins in the layout can be higher than the clock period. In order to avoid performance penalties wires are pipelined using latches. However the throughput of the system may be altered due to the presence of loops in the logic netlist. In this paper we address the problem of floorplanning a large design with interconnect pipelining and inserting throughput in the cost function of the floorplanning algorithm. The throughput results obtained on a series of benchmarks are then validated using a simple router that places flipflops along the nets built with an heuristical minimum rectilinear steiner tree.
- L.P. Carloni et alii, A Methodology for "Correct-by-Construction" Latency Insensitive Design", Proc. ICCAD 99, pp. 309--315.]] Google Scholar
Digital Library
- L.P. Carloni and A.L. Sangiovanni-Vincentelli, Performance Analysis and Optimization of Latency Insensitive Protocols, Proc. DAC 00, pp. 361--367.]] Google ScholarDigital Library
- L.P. Carloni, K.L. McMillan and A.L. Sangiovanni-Vincentelli, Theory of Latency-Insensitive Design, IEEE TCAD, vol. 20, No. 9, Sept. 2001, pp. 1059--1076.]]Google ScholarDigital Library
- J. Cong and S.K. Lim, "Physical Planning with Retiming," Proc. ICCAD 2000, pp. 2--7.]] Google ScholarDigital Library
- R. Lu and C.-K. Koh, "Interconnect Planning with Local Area Constrained Retiming," Proc. DATE 2003.]] Google ScholarDigital Library
- L.P.P.P. Van Ginneken, "Buffer Placement in Distributed RC-Tree Networks for Minimal Elmore Delay," Proc. ISCC 1990, pp. 865--868.]]Google Scholar
- R. Lu et al., "Flip-Flop and Repeater Insertion for Early Interconnect Planning," Proc. DATE 2002.]] Google ScholarDigital Library
- S. Hassoun et al. , "Optimal Buffered Routing Path Constructions for Single and Multiple Clock Domain Systems," Proc. ICCAD 2002, pp. 247--253.]] Google ScholarDigital Library
- P. Cocchini, "Concurrent Flip-Flop and Repeater Insertion for High Performance Integrated Circuits," Proc. ICCAD 2002, pp. 268--273.]] Google ScholarDigital Library
- J. Cong and D.Z. Pan, "Interconnect Delay Estimation Models for Synthesis and Design Planning," Proc. ASP-DAC 1999, pp. 97--100.]]Google Scholar
- C.J. Alpert et al., "Porosity Aware Buffered Steiner Tree Construction,", Proc. ISPD 2003, pp. 158--165.]] Google ScholarDigital Library
- H. D. Lin, D. G. Messerschmitt Improving the iteration bound of finite state machines ISCAS'89 pp. 1923--1928, vol.3.]]Google Scholar
- F.R. Boyer et al., Optimal design of synchronous circuits using software pipelining techniques, ACM TODAES, vol. 6,n. 4, pp. 516--532, 2001.]] Google ScholarDigital Library
- X. Hong et al. Corner block list: an effective and efficient topological representation of non-slicing floorplan ICCAD-2000 5-9 Nov. 2000, pp. 8--12.]] Google ScholarDigital Library
- P.-N. Guo, et al. An O-tree representation of non-slicing floorplan and its applications DAC 1999, 21-25 June 1999, pp. 268--273.]] Google ScholarDigital Library
- H. Murata et al., VLSI module placement based on rectangle-packing by the sequence-pair, IEEE TCAD, Vol. 15, Issue 12, pp. 1518--1524.]]Google Scholar
- M. Moe and H.Schmit, Floorplanning of pipelined array modules using sequence pairs Proc. ISPD 2003, pp. 143--150.]] Google ScholarDigital Library
- C.W. Sham, E.F.Y. Young Routability driven floorplanner with buffer block planning Proc. ISPD 2003.]] Google ScholarDigital Library
- Y. Ma et al., "An Integrated Floorplanning with an Efficient Buffer Planning Algorithm," Proc. ISPD 2003, pp. 136--142.]] Google ScholarDigital Library
- www.cse.ucsc.edu/research/surf/GSRC/progress.html]]Google Scholar
- http://vlsicad.eecs.umich.edu/BK/parquet/]]Google Scholar
Index Terms
- Floorplanning for throughput
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