ABSTRACT
A challenge to an automated layout of analog IC starts with the insight into a high quality placement crafted by experts. It has been observed that such a placement comprises clusters corresponding to groups of matched devices and devices are placed faithfully to the drawn schema while the placement is still compacted. This paper proposes a novel device-level placement based on Sequence-Pair which includes an effective representation of clusters extracted from the schema. A key idea is to capture a topological structure of clusters in order to place clusters at as faithful positions to those in the schema. We represent this structure in terms of ABLR-relations which can be translated into Sequence-Pair. In experiments, we tested our algorithm for industrial instances and compared the results with those by manual. We showed that our results were better than manual results by, on average, 12.8% and 18.1% with respect to area and net-length.
- J. Rijmenants, J. B. Litsios, T. R. Schwarz, and M. Degrauwe, "ILAC: An Automated Layout Tool for Analog CMOS Circuits", IEEE J. of Solid-State Circuits, Vol.SC-24, No.2, pp.417--pp.425, 1989.Google ScholarCross Ref
- S. W. Mehranfar, "A Technology-Independent Approach to Custom Analog Cell Generation", IEEE Trans. Solid-State Circuits, Vol.26, No.3, pp.386--393, 1991.Google ScholarCross Ref
- J. Cohn, D. Garrod, R. Rutenbar, and L. Carley, "Analog Device-Level Automation", Kluwer Academic Publishers, 1994. Google ScholarDigital Library
- H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectangle-Packing-Based Module Placement", International Conference on Computer Aided Design 1995, pp.472--479, 1995. Google ScholarDigital Library
- H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair", IEEE Trans. Computer-Aided Design, Vol.15, No.12, pp.1518--1524, 1996. Google ScholarDigital Library
- S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani, "Module Placement on BSG-Structure and IC Layout Applications", International Conference on Computer Aided Design 1996, pp.484--pp.491, 1996. Google ScholarDigital Library
- E. Malavasi, E. Charbon, E. Felt, and A. Sangiovanni-Vincentelli, "Automation of IC Layout with Analog Constraints", IEEE Trans. on Computer-Aided Design, Vol.15, No.8, pp.923--942, 1996. Google ScholarDigital Library
- F. Balasa and K. Lampaert, "Module Placement for Analog Layout Using the Sequence-Pair Representation", Design Automation Conference 1999, pp.274--279, 1999. Google ScholarDigital Library
- K. Lampaert, G. Gielen, and W. Sabsen "Analog Layout Generation for Performance and Manufacturability", Kluwer Academic Publishers, 1999.Google Scholar
- X. Tang, D. F. Wong, "FAST-SP: A Fast Algorithm for Block Placement based on Sequence-Pair", Asia and South Pacific Design Automation Conference 2001, pp.521--526, 2001. Google ScholarDigital Library
Index Terms
- A device-level placement with multi-directional convex clustering
Recommendations
Analog placement with symmetry and other placement constraints
ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided designIn order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other ...
Simultaneous placement with clustering and duplication
DAC '04: Proceedings of the 41st annual Design Automation ConferenceClustering, duplication, and placement are critical steps in a cluster-based FPGA design flow. Clustering has a great impact on the wirelength, timing, and routability of a circuit. Logic duplication is an effective method for improving performance ...
An effective clustering algorithm for mixed-size placement
ISPD '07: Proceedings of the 2007 international symposium on Physical designPlacement is a crucial step for the VLSI circuit physical design and it has a deep impact on the overall circuit performance. Numerous clustering techniques have been proposed and applied to placement to deal with the increasing circuit sizes and ...
Comments