Ambar A. Gadkari
ABSTRACT
Verification of present day SoCs is proving to be challenging due to complex interactions among various subcomponents and IPs, with multiple clock domains and diverse bus protocols. The quality of verification depends on the precision in specifying the interaction behaviors. We propose a visual specification language called CESC (Clocked Event Sequence Chart), designed to specify interaction scenarios in SoCs. CESC provides a unique mechanism for representating multiple clock domains, based upon which event occurrences and interactions among different subcomponents can be represented. CESC has a pictorial and textual syntax, and a formal semantics to enable rigorous analysis. The semantics is based on standard notions of partial ordering and timed event traces. CESC is useful in many ways in formalizing SoC verification flows, namely, formalization of verification scenarios, synthesis of protocol checkers and consistency checking of specification versus implementation. This paper describes an algorithm to translate CESC scenarios to protocol checkers used in SoC verification flow. A few examples from industrial designs are included to illustrate the applicability of this formalism in specifying bus transactions and properties of protocols.
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Index Terms
- CESC: a visual formalism for specification and verification of SoCs
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