Ian Robertson
Skip Abstract Section
Abstract
This paper presents a top-down designer-driven design flow for creating hardware that exploits partial run-time reconfiguration. Computer-aided design (CAD) tools are presented, which complement conventional FPGA design environments to enable the specification, simulation (both functional and timing), synthesis, automatic placement and routing, partial configuration generation and control of partially reconfigurable designs. Collectively these tools constitute the dynamic circuit switching CAD framework. A partially reconfigurable Viterbi decoder design is presented to demonstrate the design flow and illustrate possible power consumption reductions and performance improvements through the exploitation of partial reconfiguration.
- Brebner, G. 1996. A virtual hardware operating system for the Xilinx XC6200. In Field Programmable Logic and Applications, Darmstadt, Germany, September 1996, R. W. Hartenstein and M. Glesner, eds. Springer-Verlag, Berlin, 327--336.]] Google Scholar
- Brebner, G. 1997. CHASTE: A hardware/software co-design testbed for the Xilinx XC6200. In Reconfigurable Architectures Workshop, Geneva, Switzerland, April 1997, R. W. Hartenstein and V. K. Prasanna, eds. IT Press, Verlag, 16--23.]]Google Scholar
- Callahan, T. J., Hauser, J. R., and Wawrzynek, J. 2000. The GARP architecture and C compiler. IEEE Computer 33, 4, 62--69.]] Google ScholarDigital Library
- Dandalis, A. and Prasanna, V. K. 2001. Configuration compression for FPGA-based embedded systems. In 9th ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, USA, February 2001, ACM Press, 173--182.]] Google Scholar
- Diana, L. and Kahn, J. M. 1999. Rate-adaptive modulation techniques for infrared wireless communications. In Proceedings of the IEEE International Conference on Communications, Vancouver, B. C., Canada, June 1999, 597--603.]]Google Scholar
- Dyer, M., Plessl, C., and Platzner, M. 2002. Partially reconfigurable cores for Xilinx virtex. In Field Programmable Logic and Applications, Montpellier, France, September 2002, M. Glesner, P. Zipf, and M. Renovell, eds. Springer-Verlag, Berlin, 292--301.]] Google Scholar
- Faura, J., Moreno, J. M., Madrenas, J., and Insenser, J. M. 1997. VHDL modelling of fast dynamic reconfiguration on novel multicontext RAM-based field-programmable devices. In Proceedings of the SIG-VHDL Spring'97 Working Conference, Toledo, Spain, April 1997, 171--177.]]Google Scholar
- Gokhale, M. B., Stone, J. M., Arnold, J., and Kalinowski, M. 2000. Stream-oriented FPGA computing in the streams-C high level language. In Proceedings of the Eighth Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, California, USA, April 2000, K. L. Pocek and J. Arnold, eds. IEEE Computer Society Press, 49--56.]] Google Scholar
- Goldsmith, A. J. and Chua, S. G. 1998. Adaptive coded modulation for fading channels. IEEE Trans. Commun. 46, 5, 595--602.]]Google ScholarCross Ref
- Guccione, S., Levi, D., and Sundararajan, P. 1999. JBits: Java-based interface for reconfigurable computing. In Military and Aerospace Applications of Programmable Devices and Technologies Conference, Laurel, MD, September 1999.]]Google Scholar
- Hagenauer, J. and Stockhammer, T., 1999. Channel coding and transmission aspects for wireless multimedia. Proc. IEEE 87, 10, 1764--1777.]]Google ScholarCross Ref
- Horta, E. L., Lockwood, J. W., Taylor, D. E., and Parlour, D. 2002. Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. In Proceedings of the 39th Design Automation Conference, Los Angeles, USA, June 2002, 343--348.]] Google Scholar
- Hutchings, B., Nelson, B., and Wirthlin, M. J., 2000. Designing and debugging custom computing applications. IEEE Design and Test of Computers 17, 1, 20--28.]] Google ScholarCross Ref
- Keller, E. 2000. JRoute: A run-time routing API for FPGA hardware. In The Seventh Reconfigurable Architectures Workshop, Cacun, Mexico, May 2000, J. Romlin, ed. Springer-Verlag, Berlin, 874--881.]] Google ScholarCross Ref
- Kwiat, K. and Debany, W. 1996. Reconfigurable logic modelling. Integrated System Design (Dec.).]]Google Scholar
- Li, Y., Callahan, T., Darnell, E., Harr, R., Kurkure, U., and Stockwood, J., 2000. Hardware--software codesign of embedded reconfigurable architectures. In Proceedings of the 37th Design Automation Conference, Los Angeles, USA, June 2000, 507--512.]] Google Scholar
- Luk, W. and McKeever, S. 1998. Pebble: A language for parameterised and reconfigurable hardware design. In Field Programmable Logic and Applications, Tallinn, Estonia, September 1998, R. W. Hartenstein and A. Keevallik, eds. Springer-Verlag, Berlin, 9--18.]] Google Scholar
- Lysaght, P. and Stockwood, J. 1996. A simulation tool for dynamically reconfigurable field programmable gate arrays. IEEE Trans. VLSI Syst. 4, 3, 381--390.]] Google ScholarDigital Library
- MacBeth, J., 2003. Dynamically Reconfigurable Intellectual Property Cores (DRIP Cores). Ph.D. Thesis, University of Strathclyde, UK.]]Google Scholar
- McKay, N. and Singh, S. 1999. Debugging techniques for dynamically reconfigurable hardware. In IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, USA, April 1999, K. L. Pocek and J. Arnold, eds., IEEE Computer Society Press, 114--122.]] Google Scholar
- McMillan, S. and Guccione, S. 2000. Partial run-time reconfiguration using JRTR. In Field Programmable Logic and Applications, Villach, Austria, August 2000, R. W. Hartenstein and H. Grunbacher, eds. Springer-Verlag, Berlin, 352--360.]] Google Scholar
- McMillan, S., Blodget, B., and Guccione, S. 2000. VirtexDS: A device simulator for Virtex. Reconfigurable Technology: FPGAs for Computing and Applications II. Proc. SPIE 4212, Bellingham, WA, November 2000.]]Google Scholar
- Randita, B. and Roy, S. K., 1999. Design and implementation of a Viterbi decoder using FPGAs. In 12th International Conference on VLSI Design, Goa, India, January 1999, 611--614.]] Google Scholar
- Robertson, I., Irvine, J., Lysaght, P., and Robinson, D. 2002a. Timing verification of dynamically reconfigurable logic for the Xilinx Virtex FPGA series. In Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 2002, M. Schlag and S. Trimberger, eds. ACM Press, 127--135.]] Google Scholar
- Robertson, I., Irvine, J., Lysaght, P., and Robinson, D. 2002b. Improved functional simulation of dynamically reconfigurable logic. In Field Programmable Logic and Applications, Montpellier, France, September 2002, M. Glesner, P. Zipf, and M. Renovell, eds. Springer-Verlag, Berlin, 152--161.]] Google Scholar
- Robinson, D. 2002. Simulation and Control of Dynamically Reconfigurable Logic Circuits. Ph.D. Thesis, University of Strathclyde, UK.]]Google Scholar
- Robinson, D. and Lysaght, P. 2000a. Methods of exploiting simulation technology for simulating the timing of dynamically reconfigurable logic. IEE Proc. Comput. Digital Tech. 147, 3, 175--180.]]Google ScholarCross Ref
- Robinson, D. and Lysaght, P. 2000b. Verification of dynamically reconfigurable logic. In Field Programmable Logic and Applications, Villach, Austria, August 2000, R. W. Hartenstein and H. Grunbacher, eds. Springer-Verlag, Berlin, 141--150.]] Google Scholar
- Shirazi, N., Luk, W., and Cheung, P. Y. K. 1998. Automating production of run-time reconfigurable designs. In Proceedings of the Sixth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, USA, April 1998, K. L. Pocek and J. Arnold, eds. IEEE Computer Society Press, 147--156.]] Google Scholar
- Singh, S. and James-Roxby, P. 2001. Lava and JBits: From HDL to bitstream in seconds. In Proceedings of the Ninth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Rohnert Park, California, USA, April 2001, K. L. Pocek and J. Arnold, eds. IEEE Computer Society Press.]] Google Scholar
- Swaminathan, S., Tessier, R., Goeckel, D., and Burleson, W. 2002. A dynamically reconfigurable adaptive Viterbi decoder. In Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 2002, M. Schlag and S. Trimberger, eds. ACM Press, 227--236.]] Google Scholar
- Trimberger, S. 1998. Scheduling designs into a time-multiplexed FPGA. In Sixth ACM International Symposium of Field Programmable Gate Arrays, Monterey, California, USA, February 1998, ACM Press, 153--160.]] Google ScholarDigital Library
- Tripp, J. L., Jackson, P. A., and Hutchings, B. L. 2002. Sea cucumber: A synthesizing compiler for FPGAs. In Field Programmable Logic and Applications, Montpellier, France, September 2002, M. Glesner, P. Zipf, and M. Renovell, eds. Springer-Verlag, Berlin, 875--885.]] Google Scholar
- Vasilko, M. 1999. DYNASTY: A temporal floorplanning based CAD framework for dynamically reconfigurable logic systems. In Field Programmable Logic and Applications, Glasgow, UK, August 1999, P. Lysaght, J. Irvine and R. W. Hartenstein, eds. Springer-Verlag, Berlin, 124--133.]] Google Scholar
- Vasilko, M. and Cabanis, D. 1999. A technique for modelling dynamic reconfiguration with improved simulation accuracy. IEICE Trans. Fundam. Electron., Commun. Comput. Sci. E82-A, 11, 2465--2474.]]Google Scholar
- Xilinx, Inc. 2002. XAPP290: An Implementation Flow for Active Partial Reconfiguration Using 4.2i, Application Note, version 0.7, March 2002.]]Google Scholar
- Yang, J., Khandani, A. K., and Tin, N. 2002. Adaptive Modulation and Coding in 3G Wireless Systems. Technical Report UW-E&CE##2002-15, University of Waterloo, Waterloo, Ontario, Canada.]]Google Scholar
- Yeh, D., Feygin, G., and Chow, P. 1996. RACER: A reconfigurable constraint-length 14 Viterbi decoder. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, USA, April 1996, K. L. Pocek and J. Arnold, eds. IEEE Computer Society Press, 60--69.]]Google Scholar
Index Terms
- A design flow for partially reconfigurable hardware
Recommendations
Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures
Reconfigurable hybrid processor systems provide a flexible platform for mapping data-parallel applications, while providing considerable speedup over software implementations. However, the overhead for reconfiguration presents a significant deterrent in ...
Run-time reconfigurable systems for digital signal processing applications: a survey
Today's digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques ...
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP ...
Comments