skip to main content
10.1145/996566.996616acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article

A stochastic approach To power grid analysis

Published:07 June 2004Publication History

ABSTRACT

Power supply integrity analysis is critical in modern high perfor-mance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are modelled as stochastic processes and their statistical information is extracted, including correlation infor-mation between blocks in both space and time. We then propose a method to propagate the statistical parameters of the block currents through the linear model of the power grid to obtain the mean and standard deviation of the voltage drops at any node in the grid. We show that the run time is linear with the length of the current wave-forms allowing for extensive vectors, up to millions of cycles, to be analyzed. We implemented the approach on a number of grids, including a grid from an industrial microprocessor and demonstrate its accuracy and efficiency. The proposed statistical analysis can be use to determine which portions of the grid are most likely to fail as well as to provide information for other analyses, such as statistical timing analysis.

References

  1. G. Steele, D. Overhauser, S. Rochel and Z, Hussain, "Full-chip verification methods for DSM power distribution systems," in Proc. DAC, pp. 744--749, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. S. Taylor, "The challenge of designing global systems in UDSMCMOS," in Proc CICC, pp.429--435, 1999.Google ScholarGoogle Scholar
  3. A. Chandrakasan, W. J. Bowhill and F. Fox, Design of high performance microprocessor circuits, NY: IEEE Press, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. S. R. Nassif and J. N. Kozhaya, "Fast power grid simulation," in Proc. DAC, pp. 156--161, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. M. Zhao, R. V. Panda, S. S. Sapatnekar and D. Blaauw, "Hierarchical analysis of power distribution networks," in IEEE Trans. on CAD, pp. 159--168, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young and R. Ramaraju, "Model and analysis for combined package and on-chip power grid simulation," in Proc. ISLPED, pp. 179--184, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. A. Dharchoudhury, R. Panda, D. Blaauw and R. Vaidyanathan, "Design and Analysis of Power Distribution Networks in PowerPC microprocessors," in Proc. DAC, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. A. Krstic and K. Cheng, "Vector generation for maximum instan-taneous current through supply lines for CMOS circuits," in Proc. DAC, pp. 383--388, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Y. M. Jiang, T. Young and K. Cheng, "VIP--an input pattern gen-erator for identifying critical voltage drop for deep submicron designs," in Proc. ISLPED, pp. 156--161, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. H. Kriplani, F. Najm, I. Hajj, "Pattern independent maximum cur-rent estimation in power and ground buses of CMOS VLSI circuits," in IEEE Trans. on CAD, vol. 14. no. 8, pp. 998--1012, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. G. Bai, S. Bobba and I.N. Hajj, "RC power bus maximum voltage drop in digital VLSI circuits," in Proc. ISQED, pp. 205--210, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. George R. Cooper, Clare D. McGillem, Probabilistic Methods of Signal and System Analysis, Oxford Series, 1998.Google ScholarGoogle Scholar

Index Terms

  1. A stochastic approach To power grid analysis

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Conferences
      DAC '04: Proceedings of the 41st annual Design Automation Conference
      June 2004
      1002 pages
      ISBN:1581138288
      DOI:10.1145/996566
      • General Chair:
      • Sharad Malik,
      • Program Chairs:
      • Limor Fix,
      • Andrew B. Kahng

      Copyright © 2004 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 7 June 2004

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • Article

      Acceptance Rates

      Overall Acceptance Rate1,770of5,499submissions,32%

      Upcoming Conference

      DAC '24
      61st ACM/IEEE Design Automation Conference
      June 23 - 27, 2024
      San Francisco , CA , USA

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader