Toshinari Takayanagi
ABSTRACT
A processor core, previously implemented in a 0.25μm Al process, is redesigned for a 0.13μm Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applications. Deep submicron circuit design challenges, including negative bias temperature instability (NBTI), leakage and coupling noise, and L2 cache implementation are discussed.
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Index Terms
- A dual-core 64b ultraSPARC microprocessor for dense server applications
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