On behalf of the program committee, I am pleased to present this year's program for LCTES: Languages Compilers and Tools for Embedded Systems. Now in its third year as a conference, we received 120 submissions by the firm submission deadline. From those papers, 28 papers were chosen for presentation at this year's conference.Papers were submitted using the free version of CyberChair. Abstracts and full papers were uploaded, manually assigned to the program committee members, and reviewed over a 5-week period. Each paper was assigned to at least three program committee members, according to interest and areas of expertise, and outside reviews were sought where necessary.Because of the inherently interdisciplinary nature of this conference, the program committee is comprised of 23 researchers and practitioners from around the world who offer expertise across the many technical areas that address embedded systems. The general and program chairs participated in the review process, and so are counted as part of the program committee.The program committee convened on the 14th of March in Saint Louis for an all-day meeting to reach consensus on the program. Those members who had a conflict on a paper left the room for that paper's discussion. Program committee members were allowed to submit papers to this conference. Discussion of those papers was conducted at the very end of the meeting, after the status of all other papers was determined. Papers authored by program committee members were judged by the same, high standards applied to all submissions. At the end of the day's meeting, we accepted 28 papers for this year's program from the 120 submissions--an acceptance rate of 23%. Unfortunately, many fine papers could not be accommodated in this year's program.The composition of the program before you is a reasonable sample of the areas in which we received submissions. Sessions on program optimization, cache and other architectural features, benchmarking and software tool synthesis show the ongoing vitality of those areas. Notably, there are two sessions on power management, indicative of the growing importance of that area.
Proceeding Downloads
GraalBench: a 3D graphics benchmark suite for mobile phones
In this paper we consider implementations of embedded 3D graphics and provide evidence indicating that 3D benchmarks employed for desktop computers are not suitable for mobile environments. Consequently, we present GraalBench, a set of 3D graphics ...
Modeling and simulating electronic textile applications
This paper describes our design of a simulation environment for electronic textiles (e-textiles) and our experiences with that environment. This simulation environment, based upon Ptolemy II, enables us to model a diverse range of areas related to the ...
Spinach: a liberty-based simulator for programmable network interface architectures
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are common to all programmable environments (e.g., ALUs, control and data paths,...
NDL: a domain-specific language for device drivers
Device drivers are difficult to write and error-prone. They are usually written in C, a fairly low-level language with minimal type safety and little support for device semantics. As a result, they have become a major source of instability in operating ...
Asynchronous software thread integration for efficient software
The overhead of context-switching limits efficient scheduling of multiple concurrent threads on a uniprocessor when real-time requirements exist. Existing software thread integration (STI) methods reduce context switches, but only provide synchronous ...
A formal concurrency model based architecture description language for synthesis of software development tools
Rapidly increasing design and manufacturing non-recurring engineering (NRE) costs are prompting a shift in electronic design from hardwired application specific integrated circuits (ASICs) to the use of software on programmable platforms. However, in ...
Procrastination scheduling in fixed priority real-time systems
Procrastination scheduling has gained importance for energy efficiency due to the rapid increase in the leakage power consumption. Under procrastination scheduling, task executions are delayed to extend processor shutdown intervals, thereby reducing the ...
Power-efficient prefetching via bit-differential offset assignment on embedded processors
Due to stringent power constraints, aggressive latency hiding approaches such as prefetching are absent in the state-of-the-art embedded processors. There are two main reasons that cause prefetching to be power inefficient. First, compiler inserted ...
Speculative software management of datapath-width for energy optimization
This paper evaluates managing the processor's datapath-width at the compiler level by means of exploiting dynamic narrow-width operands. We capitalize on the large occurrence of these operands in multimedia programs to build static narrow-width regions ...
Dynamic voltage scaling for real-time multi-task scheduling using buffers
This paper proposes energy efficient real-time multi-task scheduling (EDF and RM) algorithms by using buffers. The buffering technique overcomes a drawback of previous approaches by utilizing the slack time of a system fully. It increases the CPU ...
A trace-based binary compilation framework for energy-aware computing
Energy-aware compilers are becoming increasingly important for embedded systems due to the need to meet conflicting constraints on time, code size and power consumption. We introduce a trace-based, offline compiler framework on binaries and demonstrate ...
ESys.Net: a new solution for embedded systems modeling and simulation
The next generation of tools for embedded systems design will represent a common arena for several cooperating groups. These tools will permit system design at a high abstraction level and enable automatic refinement through several abstraction levels ...
XTREM: a power simulator for the Intel XScale® core
Managing power concerns in icroprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these ...
Feedback driven instruction-set extension
Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. Since the extension of an instruction set and its utilization are non-...
Compositional static instruction cache simulation
Scheduling in hard real-time systems requires a priori knowledge of worst-case execution times (WCET). Obtaining the WCET of a task is a difficult problem. Static timing analysis techniques approach this problem via path analysis, pipeline simulation ...
Measuring the cache interference cost in preemptive real-time systems
Caches exploits locality of references to reduce memory access latencies and thereby improve processor performance. When an operating system switches application task or performs other kernel services, the assumption of locality may be violated because ...
Adaptive code unloading for resource-constrained JVMs
Compile-only JVMs for resource-constrained embedded systems have the potential for using device resources more efficiently than interpreter-only systems since compilers can produce significantly higher quality code and code can be stored and reused for ...
Advanced control flow in Java card programming
Java Card technology simplifies the development of smart card applications by providing a high-level programming language similar to Java. However, the master-slave programming model used in current Java Card platform creates control flow difficulties ...
Generating fast code from concurrent program dependence graphs
While concurrency in embedded systems is most often supplied by real-time operating systems, this approach can be unpredictable and difficult to debug. Synchronous concurrency, in which a system marches in lockstep to a global clock, is conceptually ...
EMBARC: an efficient memory bank assignment algorithm for retargetable compilers
Many architectures today, especially embedded systems, have multiple memory partitions, each with potentially different performance and energy characteristics. To meet the strict time-to-market requirements of systems containing these chips, compilers ...
Hardware-managed register allocation for embedded processors
Most modern processors (either embedded or general purpose) contain higher number of physical registers than those exposed in the ISA. Due to a variety of reasons, this phenomenon is likely to continue especially on embedded systems where encoding space ...
A retargetable register allocation framework for embedded processors
This paper describes the FlexCC2 register allocation framework. FlexCC2 is an optimizing retargetable C compiler for embedded processors, and in particular for DSP processors. Embedded processors often contain features such as irregular and constrained ...
Link-time optimization of ARM binaries
The overhead in terms of code size, power consumption and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded world, where real-time constraints, battery life-time and production costs ...
Optimizing for space and time usage with speculative partial redundancy elimination
Speculative partial redundancy elimination (SPRE) uses execution profiles to improve the expected performance of programs. We show how the problem of placing expressions to achieve the optimal expected performance can be mapped to a particular kind of ...
Finding effective compilation sequences
- L. Almagor,
- Keith D. Cooper,
- Alexander Grosul,
- Timothy J. Harvey,
- Steven W. Reeves,
- Devika Subramanian,
- Linda Torczon,
- Todd Waterman
Most modern compilers operate by applying a fixed, program-independent sequence of optimizations to all programs. Compiler writers choose a single "compilation sequence", or perhaps a couple of compilation sequences. In choosing a sequence, they may ...
Code protection for resource-constrained embedded devices
While the machine neutral Java bytecodes are attractive for code distribution in the highly heterogeneous embedded domain, the well-documented and standardized features also make it difficult to protect these codes. In fact, there are several tools to ...
Input data reuse in compiling window operations onto reconfigurable hardware
Balancing computation with I/O has been considered as a critical factor of the overall performance for embedded systems in general and reconfigurable computing systems in particular. Data I/O often dominates the overall computation performance for ...
Flattening statecharts without explosions
We present a polynomial upper bound for flattening of UML statecharts. An efficient flattening technique is derived and implemented in SCOPE---a code generator targeting constrained embedded systems. Programs generated with this new technique are both ...
- Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems